This Release Note is for the SPI-4.2 (POS-PHY L4) v8.5 released in 10.1 IP Update 0, and contains the following information:
- New Features
- Bug Fixes
- General Information
- Known Issues
For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at: http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf
New Features in v8.5
- ISE 10.1i software support added
- Synopsys VCS simulator verilog support added
Bug Fixes in V8.5
- The Source core has a problem sending out the last credit and EOP of the last packet written into the FIFO. The data is not lost, but it will not be sent out unless another packet is written into the FIFO. The failure occurs when SrcBurstMode = 1 and SrcBurstLen > 256. (CR 453077)
- The Source Overflow signal (SrcFFOverflow_n) is asserted without an Almost Full signal (SrcFFAlmostFull_n) asserted. The failure occurs when SrcBurstMode=1, SrcBurstLen > 256 and SrcAFThresAssert is smaller than SrcBurstLen. (CR 453079)
- Version 8.5 of the SPI-4.2 Core supports the Virtex-4 and Virtex-5 families. For Virtex-II and Virtex-II Pro designs, use the latest version of the v6.x series of the SPI-4.2 Core.
- The Version 8.5 Core is compatible with ISE 10.1.
- If you are using multiple SPI-4.2 Cores in a single device, you must generate the core with a unique component name for each instance. See the "Multiple Core Instantiation" section under the "Special Design Consideration" chapter of the SPI-4.2 User Guide.
(Xilinx Answer 15500) - How do I edit the SPI-4.2 (PL4) UCF file so that the TSClk is skewed by 180 degrees in the DCM?
(Xilinx Answer 20017) - Which I/O Standards are supported for the SPI-4.2 Core?
Known Issues in v8.5
Constraints and Implementation Issues
(Xilinx Answer 20000) When implementing an SPI-4.2 design through NGDBuild, several "WARNING" and "INFO" messages appear
(Xilinx Answer 21439) When implementing an SPI-4.2 design through MAP, several "WARNING" and "INFO" messages appear
(Xilinx Answer 21320) When implementing an SPI-4.2 design through PAR, several "WARNING" and "INFO" messages appear
(Xilinx Answer 21363) PAR has problems placing components or completely routing the SPI4.2 design in my design
(Xilinx Answer 20280) Placement failures occur in PAR when the SPI-4.2 FIFO Status Signals' I/O Standard is set to LVTTL I/O
(Xilinx Answer 20040) Timing Analyzer (TRCE) reports "0 items analyzed".."
(Xilinx Answer 20319) When running implementation, undefined I/O (single-ended) defaults to LVCMOS causes WARNINGS in NGDBuild
General Simulation Issues
(Xilinx Answer 24027) Compiling XilinxCoreLib gives error: "Error-[URMI] Instances with unresolved modules remain in the design"
(Xilinx Answer 24026) When running simulation on SPI-4.2 design, Locked_RDClk (from RDClk DCM) might get de-asserted after PhaseAlignRequest
(Xilinx Answer 21319) When running timing simulation on an SPI4.2 design example, several "TDat Error: Data Mismatch" messages are reported
(Xilinx Answer 21322) When running timing simulation on a SPI4.2 design, several SETUP, HOLD, and RECOVERY violations occur
(Xilinx Answer 20030) When simulating an SPI-4.2 design, multiple warning messages are expected at the beginning of the simulation
(Xilinx Answer 15578) When simulating an SPI-4.2 (PL4) Core using NC-Verilog (by Cadence) or VCS (by Synopsys), unusual and inconsistent behaviors occur
SPI- 4.2 (PL4) v8.4 Known Issues
- The SPI-4.2 v8.4 Core is now obsolete. Please upgrade to the latest version of the core. For information on existing SPI-4.2 v8.4 issues, see (Xilinx Answer 25457).
SPI- 4.2 (PL4) v8.3 Known Issues
- The SPI-4.2 v8.3 Core is now obsolete. Please upgrade to the latest version of the core. For information on existing SPI-4.2 v8.3 issues, see (Xilinx Answer 23846).