We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 30126

9.2.04i PAR - For Virtex-5 PLL to DCM Core, PAR fails to place the PLL and DCM in the same CMT block


Keywords: PLL, DCM, Virtex5, PAR, Place, CMT, Unroutable

For Virtex-5 project, the PLL to DCM Core which can be generated by CORE Generator uses the PLL to drive the DCM directly without a BUGCTRL. Both the PLL and DCM should reside in the same CMT block because dedicated routing resources exist between them.

Cases have been seen where PAR failed to place the PLL and DCM in the same CMT block. The following warning is issued:

WARNING:Route:436 - The router has detected an unroutable situation for one or more connections. The router will finish
the rest of the design and leave them as unrouted, The cause of this behavior is either an issue with the placement
or unroutable placement constraints. To allow you to use FPGA editor to isolate the problems, the following is a list
of (up to 10) such unroutable connections:
Unroutable signal: **/<core_name>/CLKOUTDCM0_CLKIN pin: **/<core_name>/DCM_ADV_INST/CLKIN


To work around this problem, please add LOC constraints to the PLL and DCM so that they are placed into the same CMT. The following is an example:

INST "**/<core_name>/DCM_ADV_INST" LOC = "DCM_ADV_X0Y6" ;
INST "**/<core_name>/PLL_ADV_INST" LOC = "PLL_ADV_X0Y3" ;

This problem is scheduled to be fixed in ISE 10.1 Service Pack 1.

AR# 30126
Date 03/05/2008
Status Active
Type General Article