I have a NPI peripheral that attaches to a 64-bit PIM port of the MPMC controller. I have observed in hardware that when the PIM_RdFifo_Flush signal is active (1-cycle), two cycles later the PIM_RdFifo_Empty signal will go Low for one cycle. The PIM port is idle, no pending requests, at the assertion of the RdFifo_Flush. The false non-empty assertion is a problem for the FIFO read logic that monitors it.
This issue affects only designs with P_INPUT_PIPELINE == 1.
To work around this issue, the pushaddr_r signal must be synchronously reset by both the RST and Flush signals. Copy the MPMC to the project pcores directory and modify either the mpmc_data_path.v (MPMC v3) or mpmc_read_fifo.v (MPMC v4) file to match as follows:
if (P_INPUT_PIPELINE == 1) begin : gen_pushaddr_pipeline
always @(posedge Clk) begin
if (Rst | Flush) --add
pushaddr_r <= 0; --add
pushaddr_r <= pushaddr;
//push_r <= Push;
This issue has been fixed in MPMC v4.01.a, which was released in EDK 10.1, Service Pack 1.