We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 30142

LogiCORE 10-Gigabit Ethernet MAC v8.4 - Release Notes and Known Issues for ISE 10.1 Initial IP Update (IP_10.1.0)


This Answer Record contains the Release Notes for the LogiCORE 10-Gigabit Ethernet MAC v8.4 Core which was released in the ISE 10.1 Initial IP Update and includes the following: 


- New Features 

- Bug Fixes 

- Known Issues  


For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at: http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf.


New Features 


- ISE 10.1 design tools support 

- Improved timing for all families 

- Added Synopsys VCS simulator Verilog support 


Bug Fixes 


- None 


Known Issues  


1) WAN mode disabled when In-band FCS mode is enabled 


2) WAN mode not supported for Virtex-II and Virtex-II Pro families 


3) Incorrect IFG length can be seen when using WAN mode. In WAN mode over time with certain sized packets, the overall IFG length can be slightly larger or smaller than described in the specification. This is not an issue when operating in LAN mode. 


4) Transmitted IFG contains extra bytes for certain frame sizes with In-band FCS passing enabled. For more information, see (Xilinx Answer 30649)


5) After going full, RX FIFO stays full. For more information and a work-around, see (Xilinx Answer 30187)


6) In 10.1 SimPrims, the output of X_IDELAY is "X" in VCS Verilog Simulation. For more information, see (Xilinx Answer 30646)


7) In 10.1 SimPrim Post PAR timing simulation, the simulation does not always work as expected. For more information, see (Xilinx Answer 30815).

AR# 30142
Date 05/22/2014
Status Archive
Type General Article
Page Bookmarked