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AR# 30143

LogiCORE XAUI v7.3 - Release Notes and Known Issues for ISE 10.1 Initial IP Update (IP_10.1.0)


Keywords: 10, Ten, Gigabit, Ethernet, MAC, patch, installation, instruction, ip0_k, Virtex-5

This Answer Record contains the Release Notes for the LogiCORE XAUI v7.3 Core, which was released in the ISE 10.1 Initial IP Update and includes the following:

- New Features
- Bug Fixes
- Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at: http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf


New Features

- ISE 10.1 design tools support
- Virtex-5 FXT support
- Synopsys VCS simulator Verilog support
- Updated wrappers to GT11 RocketIO Wizard 1.6
- Updated wrappers to GTP Wizard 1.8
- Updated Virtex-5 GTP parameters: PMA_RX_CFG values changed to exclude second order loop filter
- Updated wrappers to GTX Wizard 1.2
- Selected family, package, and speed grade are now propagated into UCF constraint file and SCR script file

Bug Fixes

- Update GUI and documentation to reflect latest IEEE 802.3-2005 specification (CR 446847)
- Constrain MDIO interface to 2.5 MHz (CR 454881)
- Drive DCM input clock with BUFG (Virtex-5) (CR 448955)
- Reset_txsync should be synchronous (Virtex-5) (CR 452077)
- Issue an RXRESET if necessary for channel bonding (CR 432052)
Under some circumstances it is necessary to issue an
RXRESET to the Virtex-5 RocketIO to channel bond. A small circuit has
been added to the block level to reset the RocketIO when required.
- Changed Data Sheet Number from DS265 to DS266 (CR 445949)
- Remove SystemVerilog keyword from Verilog files (CR 458111)
The DRP interface contained a port with the SystemVerilog
reserved keyword "DO." The ports on this interface have been renamed
to remove the keyword.
- Virtex-4 GT11 init blocks can have glitching if not encoded as one-hot in Synplify.
This issue does not effect XST. For more information, see (Xilinx Answer 25469).

Known Issues

1. Virtex-4 Example design timing simulation fails with error, "Transmit fail: data mismatch at XAUI serial interface." For more information, see (Xilinx Answer 24678).

2. Virtex-5 Functional or Timing Simulation. In (UniSim) functional simulation or (SimPrim) timing simulation, if TXPOWERDOWN#_IN is "X," this causes GTP outputs TXN/TXP to always be "X." If TXPOWERDOWN#_IN never goes to "X," the problem is not seen. For more information, see (Xilinx Answer 24677).

3. Virtex-5 LXT ES silicon requires transmit signals between the fabric and GTP to be registered and locked down in order to meet timing. These were included in v7.0 of the XAUI core but have not been included in v7.1 or v7.2 as they are not needed for production devices. If Virtex-5 ES silicon must be targeted, the wrapper file for the GTP can be regenerated with the RocketIO wizard. Refer to (Xilinx Answer 24168) for instructions on how to generate the file.

4. In 10.1 SimPrim Post PAR timing simulation, the simulation does not always work as expected. For more information, see (Xilinx Answer 30815).

5. There have been some attribute updates to the GTX wrappers since the core was released. For more information, see (Xilinx Answer 30577).

6. The Virtex-5 XAUI example design contains default transceiver locations of X0Y0 and X0Y1 in the UCF. If the selected part or package does not contain these sites, you need to customize the UCF accordingly to ensure the design is fully placed. This causes MAP to error out for the V5FX70TFF665 package.

7. For Virtex-4 GT11 and Virtex-5 GTP near end serial PMA loopback, additional attribute changes are required that are not done by the XAUI Core. These attribute changes can be done through the DRP interface. For more details on these requirements, please consult the serial near end PMA loopback sections Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide (UG076) and Virtex-5 RocketIO GTP Transceiver User Guide (UG196):

8. For Virtex-4 GT11, under some circumstances output skew between lanes can be large. This is solved by inverting GREFCLK. This is resolved in the below patch. This change requires an additional BUFG. In addition to the patch, Max skew and delay constraints should be used for the inverted GREFCLK. For more information, see (Xilinx Answer 31702).

9. For Virtex-4 GT11, under some circumstances channel bonding can fail. This is solved by increasing CHBOND_LIMIT to 12. This is resolved in the below patch.

10. Virtex-5 GTP / GTX transceiver can require a RXCDRRESET to recover after deasserting the powerdown signal. The logic to issue RXCDRRESET after powerdown has been included in the block level in the below patch.

11. Virtex-5 GTP wizard has been changed to use BUFFERED DESKEW mode. After characterization, the use mode of the transceivers has been changed to use BUFFERED DESKEW. There are also changes to the block level to incorporate the new GTP wizard changes. This is resolved in the below patch.

To resolve issues 8, 9, 10 and 11 from the list of issues above, apply the following patch to the Xilinx ISE installation with the 10.1i Service Pack 2:


1. Install the patch by extracting the contents of the ".zip" or "tar.gz" archive to the root directory of the Xilinx ISE installation. Select the option that allows the extractor to overwrite all of the existing files and maintain the directory structure predefined in the archive.

Determine the Xilinx ISE installation directory by entering the following at the command prompt:
echo %XILINX%

UNIX or Linux
Determine the Xilinx ISE installation directory by entering the following:
echo $XILINX

NOTE: You might be required to have system administrator privileges to install the patch.

2. After installing the patch, regenerate the XAUI Core from CORE Generator. The core and supporting files produced will contain the updates mentioned above.

AR# 30143
Date 09/17/2008
Status Active
Type General Article
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