This Answer Record contains the Release Notes for the LogiCORE Gigabit Ethernet MAC v8.4 Core, which was released in the ISE 10.1 Initial IP Update. It includes the following:
- New Features
- Bug Fixes
- Known Issues
For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at: http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf
- ISE 10.1 design tools support
- Virtex-5 FXT support
- VCS simulator support
- Added support for control frames >= 64 bytes
- When using the Example Design Local Link RX FIFO, incorrect data can be read when toggling rd_dst_rdy_n. For more information, see (Xilinx Answer 29660).
- In 10.1 SimPrims, the output of X_IDELAY is "X" in VCS Verilog Simulation. For more information, see (Xilinx Answer 30646).
- In 10.1 SimPrim Post PAR timing simulation, the simulation does not always work as expected. For more information, see (Xilinx Answer 30815).