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AR# 30146

LogiCORE Tri-Mode Ethernet MAC v3.5 - Release Notes and Known Issues for ISE 10.1 Initial IP Update (IP_10.1.0)

Description

This Answer Record contains the Release Notes for the LogiCORE Tri-Mode Ethernet MAC v3.5 Core, which was released in the ISE 10.1 Initial IP Update, and includes the following:

- New Features

- Bug Fixes

- Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at: http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf.

Solution

New Features

- ISE 10.1 design tools support

- Virtex-5 FXT support

- VCS simulator support

- Added support for control frames >= 64 bytes

Bug Fixes

- Incorrect data can be read out of the RX LL FIFO if rd_dst_rdy_n has been deasserted, see (Xilinx Answer 29660).

- A pipelined version of the frame_in_fifo signal is now used to ensure valid frame data.

- Missing period constraint on rx_clock added, see (Xilinx Answer 29935).

- This might affect some families implementing GMII (CR 456603).

Known Issues

- The device utilization table in the Data Sheet reports 2 block RAM when the Clock Enable option is not used. The core netlist no longer uses these block RAM. At the block-level wrapper file for the core, no block RAM are used in any of the configurations.

- When using RGMII and Spartan-3 family devices, the example design has a missing period contraint. For more information, see (Xilinx Answer 30644).

- In 10.1 SimPrims, the output of X_IDELAY is "X" in VCS Verilog Simulation. For more information, see (Xilinx Answer 30646).

- In 10.1 SimPrim Post PAR timing simulation, the simulation does not always work as expected. For more information, see (Xilinx Answer 30815).

AR# 30146
Date Created 03/14/2008
Last Updated 12/15/2012
Status Active
Type General Article