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AR# 30148

Embedded Tri-mode Ethernet MAC Wrapper (Virtex-4) v4.6 - Release Notes and Known Issues for ISE 10.1 Initial IP Update (IP_10.1.0)

Description

This Answer Record contains the Release Notes for the LogiCORE Embedded Tri-mode Ethernet MAC Wrapper v4.6 that was released in the ISE 10.1 Initial IP Update. It includes the following:

- New Features

- Bug Fixes

- Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at: http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf

Solution

New Features

- ISE 10.1i software support

- New 16-bit client example design runs at 2 Gbps

- Updated Virtex-4 GT11 reset/initialization state machines to match the latest recommendations

Bug Fixes

- When using the Example Design Local Link RX FIFO, incorrect data can be read when toggling rd_dst_rdy_n. For more information, see (Xilinx Answer 29660).

- Virtex-4 GT11 init blocks can have glitching if not encoded as one-hot in Synplify. This issue does not affect XST. For more information, see (Xilinx Answer 25469).

- In the simulation scripts, $Xilinx has been changed to $env(Xilinx) for better TCL support.

- Addresses entered in for UNICAST_PAUSE_ADDRESS in the GUI now are written correctly to the wrapper.

- Virtex-4 GT11 init blocks can have glitching if not encoded as one-hot in Synplify. This issue does not effect XST. For more information, see (Xilinx Answer 25469).

Known Issues

1. When using 16-bit 1000BASE-X interface functional simulation could fail with incorrect data read out of the TEMAC. This will be fixed with updated UniSim libraries in 10.1i. This is not an issue when using any of the 8-bit interface.

2. In 10.1 SimPrims the output of X_IDELAY is 'X' in VCS Verilog Simulation. For more information, see (Xilinx Answer 30646).

3. In 10.1 SimPrim Post-PAR timing simulation, the simulation does not always work as expected. For more information, see (Xilinx Answer 30815).

4. Loopback might fail in 1000BASE-X or SGMII mode. For more information and a work-around, see (Xilinx Answer 30574).

5. (Xilinx Answer 32186) 16-bit 1000BASE-X Verilog RX FIFO could incorrectly overflow.

6. (Xilinx Answer 31860) Virtex-4/Virtex-5 Embedded Tri-Mode Ethernet MAC - Problems switching from 10/100 Mbps to 1G GMII operation

AR# 30148
Date Created 03/12/2008
Last Updated 12/15/2012
Status Active
Type General Article