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AR# 30149

Virtex-5 Embedded Tri-mode Ethernet MAC Wrapper v1.4 - Release Notes and Known Issues for ISE 10.1 Initial IP Update (IP_10.1.0)

Description

Keywords: Virtex-5, TEMAC, tri-speed, patch, installation, instruction, v1.4, ip0_l, IP Update 0, LXT

This Answer Record contains the Release Notes for the LogiCORE Embedded Tri-mode Ethernet MAC Wrapper v1.4, which was released in the ISE 10.1 Initial IP Update and includes the following:

-General Information
- New Features
- Bug Fixes
- Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at: http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf

Solution

General Information

- Supports automatic generation of HDL wrapper files for the Virtex-5 LXT Tri-Mode Ethernet MAC
- Instantiates user-configurable Ethernet MAC physical interfaces (GMII, MII, RGMII, SGMII and 1000Base-X PCS/PMA configurations are supported)
- Provides a FIFO-based example design
- Provides a demonstration testbench for the selected configuration

New Features

- ISE 10.1 software support
- Support added for Virtex-5 FXT devices
- Synopsys VCS Simulator Verilog support added
- Updated Virtex-5 GTP parameters; PMA_RX_CFG values changed to exclude 2nd order loop filter

Bug Fixes

- CR452225. Buffer over/underflow during AN resets GTP and elastic buffer which causes AN to never complete. For more information, see (Xilinx Answer 29630).
- CR450650. Incorrect data can be read out of the RX LL FIFO if rd_dst_rdy_n has been deasserted. For more information, see (Xilinx Answer 29660).

Known Issues

- Virtex-5 LXT/SXT ES silicon requires transmit signals between the fabric and GTP to be registered and locked down to meet timing. These registers are not included in version v1.4 of the core. If LXT/SXT ES silicon is being used, the RocketIO wrapper files can be regenerated with the GTP wizard.

- Virtex-5 Functional or Timing Simulation. In (UniSim) functional simulation or (SimPrim) timing simulation, if TXPOWERDOWN#_IN is "X," this causes GTP outputs TXN/TXP to always be "X." If TXPOWERDOWN#_IN never goes to "X," the problem does not occur. For more information, see (Xilinx Answer 24677).

- In 10.1 SimPrim, the output of X_IDELAY is 'X' in VCS Verilog simulation. For more information, see (Xilinx Answer 30646).

- In 10.1 SimPrim, Post PAR timing simulation, the simulation does not always work as expected. For more information, see (Xilinx Answer 30815).

- There have been some attributes updates to the GTX wrappers since the core was released. For more information, see (Xilinx Answer 30577).

- The VLAN, LTCHECK, HALF-DUPLEX, and INBANDFCS GUI selections are not always set correctly in HDL wrappers. For more information and a work-around, see (Xilinx Answer 30816).

- In 1000BASE-X or SGMII mode, the GUI allows you to select the default for the PHY reset and power-down attributes. This GUI selection does not actually have any effect on the generated wrappers. In 1000BASE-X or SGMII mode, the wrappers always set the PHY reset and power-down attributes to FALSE.

AR# 30149
Date Created 03/14/2008
Last Updated 04/28/2008
Status Active
Type General Article