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AR# 30151

LogiCORE Fibre Channel Arbitrated Loop v2.3 - Release Notes and Known Issues for ISE 10.1 Initial IP Update (IP_10.1.0)

Description

This Answer Record contains the Release Notes for the LogiCORE Fibre Channel Arbitrated Loop v2.3, which was released in the ISE 10.1 Initial IP Update, and includes the following: 

 

- New Features 

- Bug Fixes  

- Known Issues  

 

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at: http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf

Solution

New Features  

 

- ISE 10.1i software support 

 

Resolved Issues  

 

- Multispeed core simulation for Virtex-5 GTP - required enhancement to example design (CR 445672). 

- Removed glbl.v from Verilog timing simulation - the glbl module now appears in the netlist (CR 449546). 

- Updated GTP parameters - PMA_RX_CFG values changed to exclude 2nd order loop filter (CR 453094).  

- The coding in the example designs for Virtex-5 could cause CRC errors to go undetected 50 percent of the time in hardware. For more information, see (Xilinx Answer 29985). (CR 456596)  

 

Known Issues 

 

- For Virtex-II Pro board designs to avoid BER failures, it is important to ensure that boards meet Virtex-II Pro MGT specifications. For more information, see (Xilinx Answer 25035).  

 

- Spurious RAMB Collisions during simulation - warnings may be seen during simulation which may be safely ignored. (CR 451722)

AR# 30151
Date Created 03/14/2008
Last Updated 05/22/2014
Status Archive
Type General Article