AR# 30174

LogiCORE Interleaver/De-Interleaver - Release Notes and Known Issues

Description

This Answer Record contains the Release Notes and Known Issues list for the CORE Generator LogiCORE IP Interleaver/De-Interleaver core.The following information is listed for each version of the core:

  • New Features
  • Resolved Issues
  • Known Issues

LogiCORE IPInterleaver/De-Interleaver Lounge:
http://www.xilinx.com/products/ipcenter/DO-DI-INTERLEAV.htm

Solution

General LogiCORE Interleaver/De-Interleaver Issues

  • None

LogiCORE Interleaver/De-Interleaver v7.1

Initial Release in Vivado 2012.2

Supported Devices (Vivado)

  • All 7 Series Devices

New Features

  • Ongoing new device support.

Resolved Issues

  • N/A

Known Issues

  • N/A

LogiCORE Interleaver/De-Interleaver v7.0

Initial Release in ISE Design Suite 13.3

Supported Devices (ISE)

  • All 7 Series Devices
  • All Virtex-6 Devices
  • All Spartan-6 Devices

Supported Devices (Vivado)

  • All 7 Series Devices

New Features

  • AXI4-Stream Interface
  • FD Abort functionality removed
  • Reset is now active low, and overrides Clock Enable
  • EXTERNAL_MEMORY_LATENCY XCO added

Resolved Issues

  • N/A

Known Issues

  • N/A

LogiCORE Interleaver/De-Interleaver v6.0

Initial Release in ISE Design Suite12.1

New Features

  • ISE 12.1 software support
  • Support for Virtex-6, Virtex-6Q, Virtex-6 Low Power, Spartan-6, Spartan-6Q, Spartan-6 Low Power deviceswith ISE 12.1 software

Resolved Issues

  • CR 418254 GUI range checking issues resolved
  • CR 457270 Resolved external address generation problem that could occur when config_sel was all 1's

Known Issues

  • LogiCORE Interleaver/De-Interleaver v6.0 - Why does the Unisim model of the core not compile? See (Xilinx Answer 35367)

LogiCORE Interleaver/De-Interleaver v5.1

Initial Release in ISE 10.1

New Features

  • Support added for Spartan-3A DSP FPGA

Resolved Issues

  • CR 425954 XCD file corrected to allow support for Virtex-II Pro-X family.

Known Issues

  • The Product page and the data sheet (DS250) do not mention support for Spartan-3A and Spartan-3A DSP. Why? See (Xilinx Answer 31859).
  • Does the Interleaver/De-Interleaver support other standards e.g. 3GPP-GSM? See (Xilinx Answer 32255).

LogiCORE Interleaver/De-Interleaver v5.0 rev1

Initial Release in ISE 9.2i IP Update 1

New Features

  • Same as v5.0

Resolved Issues

  • Fixed Hardware Timeout Issue

Known Issues

  • Same as v5.0

LogiCORE Interleaver/De-Interleaver v5.0

Initial Release in ISE 8.2i IP Update 2

New Features

  • Support added for Virtex-5 FPGA

Resolved Issues

  • N/A

Known Issues

LogiCORE Interleaver/De-Interleaver v4.0

Initial Release in ISE 6.2i IP Update 3

New Features

  • Support added for Virtex-4 FPGA

Resolved Issues

  • CR 186001: Corrected "maximum branch length constant" issue.

Known Issues

  • 6.2i CORE Generator - Core generation fails with "WARNING: Cannot generate the < Core_type > core, < Core_Name >, because the license file < name_ver.lic > could not be found". See (Xilinx Answer 19519).
  • Interleaver fails in MAP for Virtex-II Pro FPGA parts. See (Xilinx Answer 14124).

LogiCORE Interleaver/De-Interleaver v3.1

Initial Release in ISE 6.1i IP Update 1

New Features

  • Ability to swap between multiple configurations "on the fly".
  • New Architecture option allows you to control whether look-up table ROMs or logic circuits are used to compute some of the internal results in the core.
  • Option to use external symbol memory.
  • Optimized implementation and reduced size when FDO and other optional pins are selected.

Resolved Issues

  • N/A

Known Issues

  • 6.2i CORE Generator - Core generation fails with "WARNING: Cannot generate the < Core_type > core, < Core_Name >, because the license file < name_ver.lic > could not be found". See (Xilinx Answer 19519).

LogiCORE Interleaver/De-Interleaver v3.0

Initial Release in ISE 5.2i IP Update 2

New Features

  • Support added for Spartan-3 FPGA
  • Evaluation version now uses Hardware Timeout.
  • Core generation uses new licensing scheme.

Resolved Issues

  • N/A

Known Issues

  • 6.2i CORE Generator - Core generation fails with "WARNING: Cannot generate the < Core_type > core, < Core_Name >, because the license file < name_ver.lic > could not be found". See (Xilinx Answer 19519).

LogiCORE Interleaver/De-Interleaver v2.0

Initial Release in ISE 4.2i IP Update 2

New Features

  • Support added for Virtex-II Pro and Spartan-II E FPGA
  • Choice of Forney Convolutional or Rectangular Block architecture.

Resolved Issues

  • N/A

Known Issues

  • Simulation error: "/test/sid_v2/beh/inter_blk_rec.v(179): Instantiation of 'glbl' failed (design unit not found)...". See (Xilinx Answer 14373).
  • When generating FEC cores, the CORE Generator program hangs on HP Platforms. See (Xilinx Answer 14127).
  • "ERROR:Xst:1031 - my_core.v Line 245. Module 'C_REG_FD_V5_0' not defined...". See (Xilinx Answer 14341).

LogiCORE Interleaver/De-Interleaver v1.1

Initial Release in ISE 4.1i IP Update 1

New Features

  • N/A

Resolved Issues

  • CR 139969 : Fix to undefined output due to internal address clash in back-annotated simulation.

Known Issues

LogiCORE Interleaver/De-Interleaver v1.0

Initial Release in ISE 3.3 IP Update 4

New Features

  • Forney convolutional type architecture.
  • Fully synchronous design using a single clock.
  • Parameterizable number of branches.
  • Parameterizable branch lengths.
  • Symbol size from 1 to 256 bits.

Bug Fixes

  • N/A

Known Issues

- N/A

AR# 30174
Date 07/23/2012
Status Active
Type Release Notes
IP