Solution
General LogiCORE Reed Solomon Decoder Issues
I cannot find the Verilog behavioral simulation model for the Reed Solomon Decoder; when performing a Verilog behavioral simulation, I receive "Error: (vsim-3033) ... The design unit was not found," see (Xilinx Answer 21679).
LogiCORE Reed Solomon Decoder v8.0
New Features
- ISE Design Suite13.3 support
- AXI4-Stream interfaces
- Option to not output check symbols
Supported Devices
- Virtex-7
- Virtex-7 -2L
- Virtex-7 -2G
- Virtex-7 XT*
- Kintex-7
- Kintex-7 -2L
- Artix-7*
- Zynq-7000*
- Virtex-6 XC CXT/LXT/SXT/HXT
- Virtex-6 XQ LXT/SXT
- Virtex-6 -1L XC LXT/SXT
- Virtex-6 -1L XQ LXT/SXT
- Spartan-6 XC LX/LXT
- Spartan-6 XA LX/LXT
- Spartan-6 XQ LX/LXT
- Spartan-6 -1L XC LX
- Spartan-6 -1L XQ LX
Resolved Issues
Known Issues (ISE)
Known Issues(Vivado) - (Xilinx Answer 52205) Why do I get an Application Error when trying to synthesize using 2012.2 Vivado Synthesis?
LogiCORE Reed Solomon Decoder v7.1
- Initial Release in ISE Design Suite12.2
New Features
- ISE Design Suite 12.2 support
- Support returned for Spartan-6 devices
Resolved Issues
Known Issues
LogiCORE Reed Solomon Decoder v7.0
- Initial Release in ISE Design Suite 11.2
New Features
- ISE Design Suite11.2 software support
- Virtex-6 and Spartan-6 FPGA support
- Increased maximum number of check symbols to 256
- Asynchronous reset input removed. Use SR input for synchronous reset if required. Core does not need to be reset in normal operation.
- Area optimization is only selectable for Virtex-5 family
- Reduced generation time
Bug Fixes
- CR469216
- Description: PUNC_SEL pin width wrong in asy file and GUI
- Resolution: PUNC_SEL width in asy file and GUI now matches netlist
Known Issues
LogiCORE Reed Solomon Decoder v6.1
- Initial Release in ISE software
New Features
- Support added for Spartan-3A DSP devices
Bug Fixes
- CR 431627 - Evaluation version generated even with full license in place
Known Issues
- Incorrect .VHO file created for Reed/Solomon Decoder when no license is found, see (Xilinx Answer 30542).
LogiCORE Reed Solomon Decoder v6.0
- Initial Release in ISE software
New Features
Bug Fixes
- Full License Hardware Time out Issue resolved
Known Issues
LogiCORE Reed Solomon Decoder v6.0
- Initial Release in ISE software
New Features
- Support added for Virtex-5 and Spartan-3A FPGA
- Support removed for Virtex and Spartan-II. Please use the v5.1 core if targeting these architectures.
- Support added for ISE software 8.2i
- Variable check symbol input added (R_IN)
- New control and monitoring signals added:
- Marker bits (MARK_IN, MARK_OUT)
- INFO_END output
- Bit Error Statistics outputs (BIT_ERR_0_TO_1, BIT_ERR_1_TO_0, BIT_ERR_RDY)
- Now uses XST to elaborate the design
- Unisim simulation model for both VHDL and Verilog languages
Bug Fixes
Known Issues
LogiCORE Reed Solomon Decoder v5.1
- Initial Release in ISE 6.3i IP Update 4
New Features
- Support for multi-channel implementation which improves core efficiency for high speed applications such as OC-192
- Updated puncturing option which improves core efficiency for standards such as IEEE802.16d
- New self-recovery mode feature
Bug Fixes
Known Issues
- Why do I receive a warning that the processing delay 142 for 2 channel decoder is incorrect? See (Xilinx Answer 21769).
LogiCORE Reed Solomon Decoder v5.0
- Initial Release in ISE 6.2i IP Update 2
New Features
- Support added for Virtex-4 FPGA
Bug Fixes
Known Issues
LogiCORE Reed Solomon Decoder v4.1
- Initial Release in ISE 6.1i IP Update 1
New Features
- New option for variable N input
- True clock enable
- RFFD output added
- Sync mode parameter removed. Now defaults to "start_pulse".
- "Create RPM" option disabled for Spartan-3
- Verilog model no longer available. Please use the VHDL model, or use "netgen" to generate a Verilog model from a post-Ngdbuild NGD netlist.
Bug Fixes
Known Issues
LogiCORE Reed Solomon Decoder v4.0
- Initial Release in ISE software 5.2i IP Update 2
New Features
- Support added for Spartan-3 FPGA
- Support for new license-based full system evaluation flow
Bug Fixes
Known Issues
Why do I get a PAR warning about the placement constraints when the "Create RPM" option is selected? See (Xilinx Answer 16931).
LogiCORE Reed Solomon Decoder v3.0
- Initial Release in ISE software 4.2ik IP Update 2
New Features
- Support added for Virtex-II Pro and Spartan-IIE FPGA
- Added optimization parameter which results in increased speed in exchange for a small increase in area.
Bug Fixes
- Data sheet updated
- Timescale directives ('timescale 1ns/10ps) added to Verilog Behavioral model
Known Issues
LogiCORE Reed Solomon Decoder v2.0
- Initial Release in ISE software 3.3 IP Update 4.
New Features
- Fully synchronous design using a single clock
- Support for continuous input data with no gap between code blocks
- Symbol size from 3 to 12 bits
- Code block length variable up to 4095 symbols
- Supports shortened codes
- Supports error and erasure decoding
- Parameterizable number of errors corrected
- Supports any primitive field polynomial for a given symbol size
- Counts number of errors correct and flags failures
- User-selectable control signal behavior
Bug Fixes
Known Issues
- Placer does not obey RPM constraints in a Reed-Solomon core. See (Xilinx Answer 11506).
- Reed Solomon Encoder and Decoder cores do not list Spartan-II FPGA as a supported device, see (Xilinx Answer 11340).
- ERROR:" Could not locate Project core xilinx_reed-solomon_decoder|xilinx|virtex+xc4000+spartan|1.0," see (Xilinx Answer 11238).