Basically the PCIe Tx side of the link needs to know how much room is available in the Rx side of the link before sending data. This is the flow control method used for a packet-based protocol. Therefore, the Rx side of the PCIe link advertises how much room its receive FIFO has by advertising credits. There are three FIFOs in the Rx side of the link: a completion FIFO, posted FIFO and non-posted FIFO. Credits are advertised for each one of these FIFOs from the Rx side every so often.
In our case the Root Complex is the Rx side of the PCIe link and it advertises zero credits for its completion FIFO (saying the FIFO is full). While the Root Complexs completion FIFO is full, it sends a read request to the plbv46_pcie_v2_00_a bridge asking for a chunk of data. As the requested data makes its way back from memory, onto the plb and into the plbv46_pcie_v2_00_a bridge, it begins to fill up the bridge Tx FIFO. The Tx FIFO fails to see the zero credits advertised from the Root Complex and fails to throttle back the requested data from plb and overflows.
The corrected packetfifoctl.v file that fixes this issue is available at:
Please Unzip and replace the existing 'packetfifoctl.v' file in the pcore/hdl/verilog directory of the EDK repository ( i.e C:Xilinx\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v1_00_a\hdl\verilog) with this new patch.
The issue will be fixed in the plbv46_pcie_v2_01_a version, in the next release of the EDK. It will be available at: