Page 152 states that PPC405 does not perform speculative data loads, but can speculatively fetch instructions.
Page 148: Note that if CRC0[LWL]=1 and the target non-cacheable region is also marked as guarded, the DCU will request only the data requested by the CPU.
In other words, it is saying that guarding data does have an effect here when it should not.
This clarification regards the way PPC405 in Virtex-II Pro and Virtex-4 accesses memory via its DPLB interface during data loads. As indicated in the PowerPC Processor Reference Guide (UG011), the PPC405 does not perform speculative data loads. Specifically, this means that the processor will not issue a read on the DPLB where the requested address space (double-word, cache-line, etc.) does not contain any data required by the sequential-execution model. However, the processor may issue a data cache-line read where the line contains data in excess of the required data, but only under certain conditions. Data cache-line reads to non-cached memory regions may occur only when the load-word-as-line bit (CCR0[LWL]) is set and the guarded storage attribute (SGR register or the G field of the TLB) is not set. Otherwise, the processor accesses non-cached memory using single-unit data reads with byte-enables appropriately set to access only the required data. (Note that the guarded storage attribute is also used to prevent speculative fetches via the IPLB interface.)