This Answer Record contains a tactical patch for MicroBlaze version 6.00.b.
A patch has been created for MicroBlaze version 6.00.b. The patch works only with EDK 10.1 and is not included in any service packs. All of the fixes in this patch are mainstream in MicroBlaze version 7.10.
1. Download the patch at:
2. Unzip the contents of the patch into your unified Xilinx installation directory and overwrite all existing files.
- Corrected interrupt occurring after interrupts have been disabled.
- Do not allow interrupts during exception handling.
- Allow use of 32 KB caches for Virtex-5 targets.
- Ensure that synchronized reset is used for all flip-flops.
- Corrected reading of BTR when FPU is enabled.
- Allow external break to occur also when interrupts are disabled.
- Corrected reading of PVR from Xilinx Microprocessor Debugger.
- Changed 64-bit multiplication to avoid incorrect result for some operand values.
- Avoid incorrectly setting FSR on an interrupted floating-point instruction.
- Ensure that exceptions following an interrupt or other exceptions are correctly discarded.
- Changed signed integer division to avoid incorrect result under certain circumstances.
- Avoid incorrect memory access when single-stepping load or store in Xilinx Microprocessor Debugger.
- Corrected setting of DZ bit in MSR for interrupted integer division instructions.
- Ensure that Xilinx Microprocessor Debugger always stops on watchpoints.
- Avoid stalling execution due to write cache instruction conflict with cache data read.
- Block hardware breakpoint detection during debug stop to avoid false breakpoints.