Release Notes and Known Issues in System Generator for DSP 10.1.00
System Generator for DSP 10.1.00 is a major update. Please read the documentation. It answers questions you might have about changes to the functionality or the look from previous versions of System Generator for DSP. The System Generator User Guide is accessible in PDF format at: http://www.xilinx.com/ise/optional_prod/system_generator.htm
System Generator Enhancements System Generator / Project Navigator Integration System Generator designs can now be more easily incorporated into a larger design inside of Project Navigator by using a new source type in Project Navigator. The System Generator design can also be launched from Project Navigator. DCM Support System Generator now provides the option to automatically include a DCM in a design. Although the optional DCM is abstracted away from the designer, the generated design will leverage DCMs available in the silicon. An alternative option exposes the clock ports at the top level for manual connection to a DCM. Dual Asynchronous-Clock Support for PLB46 This capability gives the designer additional flexibility by allowing the DSP and embedded processing portions of a design to run at different clock rates. Run Time Speed Improvements - Up to 2x faster first time initialization of a simulation - >10x faster initialization when loading the Xilinx Blockset in the Simulink Library Browser M-Based HW Co-Simulation System Generator models compiled for HW Co-Simulation can now be embedded, configured and utilized in a MATLAB M-code script; allowing for calls into hardware to be made from MATLAB.
Xilinx DSP Blockset Enhancements FFT 5.0 Update to existing block which now includes cyclic prefix insertion FIR Compiler 3.2 Update which now includes support for Virtex-II and Spartan-3A. Reset Generator New block that produces synchronized downsampled reset signals which eliminates the need to manually create these signals. CIC Compiler 1.1 New block now available in System Generator.
Xilinx Block Set Issues
- Why does the DSP48 Opmode block have invalid characters reading PCIN>>17 instead of PCIN>>17? See (Xilinx Answer 30790). - Why do I receive "Error 0001: Multiple Clock Support Design Rule Check Failed" when I select DCM for my "Multirate implementation" in my model containing a FIR Compiler block? See (Xilinx Answer 30310). - I am able to generate my model using the DCM option for "Multirate Implementation" despite having blocks in my design which are listed as unsupported for the DCM. See (Xilinx Answer 30312). - Why are there mismatches in my post-translate, post-MAP, or post-PAR simulation if I use the DCM for my "Multirate Implementation"? See (Xilinx Answer 30316). - Why does the post-MAP resource estimation return zero for all resources except IOBs? See (Xilinx Answer 30675).
- When using System Generator on a 64-bit XP machine, why do I receive a message stating, "There is a problem with your Xilinx ISE installation or with your Xilinx environment variable" and "could not run java.exe"? See (Xilinx Answer 29512). - Why do I receive "Error occurred while installing the Microsoft Network Monitor driver (NetMon)" during installation of WinPcap? See (Xilinx Answer 30297). - When I try to run System Generator for DSP TrendMicro's virus scanner flags PPEthernetCosimEngine.dll as a virus. See (Xilinx Answer 30512). - Why do I receiver the message "MATLAB is not installed" when I try to launch my System Generator project from ISE? See (Xilinx Answer 30313). - Simulation does not use the automatically generated Verilog testbench and stimulus files. See (Xilinx Answer 30308). - If my design does not use the full rate system clock and the DCM option is used for "Multirate Implementation", I get mismatches in my behavioral simulation. See (Xilinx Answer 30317). - Generation can fail when the Simulation Stop Function is defined for a model. See (Xilinx Answer 18623). - Why do I see an instantiated register called "xlpersistentdff" in a System Generator for DSP design? See (Xilinx Answer 24257). - JTAG Hardware Co-Sim with non-Xilinx parts in the chain causes error. See (Xilinx Answer 19599). - Why do I receive "Error 0001: caught standard exception" error when using IBM Clear Case? See (Xilinx Answer 24263). - Why do post-PAR simulation mismatches occur when running a design at faster than 200 MHz? See (Xilinx Answer 24268). - I cannot generate an NGC, Bitstream, Timing Analysis, or Hardware in the Loop target when using Synplify as my synthesis tool. Why? See (Xilinx Answer 24273). - When my model is opened with MATLAB 2006b from Windows Explorer by double-clicking the model, an internal error occurs when I try to simulate. See (Xilinx Answer 24867). - Why are there simulation mismatches at the beginning of the HDL simulation generated from System Generator for DSP when Synplify is used for synthesis? See (Xilinx Answer 29170). - Why does the design fail to generate when using a FIFO block, From FIFO block, or To FIFO block in the design, and the target path is more than 160 characters? See (Xilinx Answer 23614).