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AR# 30295

10.1 EDK, MPMC v4.00.a - BitGen dangling pins and gated clocks warnings with MIG Spartan-3 PHY

Description

Keywords: warning, PhysDesignRules, 372, 1060, gated, clock

During bitstream generation (BitGen) of a Spartan-3 MPMC design, multiple instances of the following warnings occur. Can they be ignored?

Running DRC.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/dqs_de
layed_col0<1> is sourced by a combinatorial pin. This is not good design
practice. Use the CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:1060 - Dangling pins on
block:<mpmc_core_0/mpmc_data_path_0/gen_write_fifos[0].ge
n_fifos.mpmc_write_fifo_0/gen_fifo_bram.mpmc_bram_fifo_0/gen_brams_normal.gen
_normal.gen_brams[0].bram/gen_ramb16_s36_s36.bram/DDR_SDRAM/DDR_SDRAM/mpmc_co
re_0/mpmc_data_path_0/gen_write_fifos[0].gen_fifos.mpmc_write_fifo_0/gen_fifo
_bram.mpmc_bram_fifo_0/gen_brams_normal.gen_normal.gen_brams[0].bram/gen_ramb
16_s36_s36.bram.A>:<RAMB16_RAMB16A>. The block is configured to use input
parity pins. There are dangling output parity pins.
DRC detected 0 errors and 5 warnings.
Creating bit map...
Saving bit stream in "system.bit".
Bitstream generation is complete.
Done!

Solution

Yes, these warnings can be ignored. They occur due to the dynamic LUT delay chains that are utilized in the MIG Spartan-3 PHY.
AR# 30295
Date Created 02/22/2008
Last Updated 02/22/2008
Status Active
Type General Article