When I try to generate my design containing a FIR Compiler block with "Clock Generator (DCM)" selected for "Multirate Implementation" I get "Error 0001: Multiple Clock Support Design Rule Check Failed" even though the design meets all the criteria for using a DCM to generate the required clocks.
This is a known issue in System Generator 10.1.00. The only way to work around this issue is to select the CE option for "Multirate Implementation."
This issue does not affect designs that do not contain the FIR Compiler block.
This will be fixed in a future release of System Generator.
For a listing of all System Generator for DSP known issues, see (Xilinx Answer 29595).