Keywords : BUFGCE, VHDL, UNISIM, model
When I perform a VHDL simulation using the BUFGCE primitive, I can see that the clock is not shown on the output (O) until a rising clock edge later if the enable signal (CE) is asserted after a falling edge of the input clock (I). How can I resolve this problem?
This is a known issue and the model will be fixed in 10.1 Sp2. If you need a solution prior to the service pack, please contact Xilinx Technical Support http://www.xilinx.com/support/mysupport.htm.