Where can I find more information on the EDID EEPROMs on the VSK?
You can find the EDID information on page 34 of UG235, under the Display Data Channel section.
And also in the VSK Schematic.
There are 2 EEPROMs, and several sets of signals.
1. There is an EEPROM connected to the DVI input J1 through signals AD9887_DDC_CLOCK and AD9887_DDC_DATA, which would connect to a source such as a PC. This EEPROM can be written to by the FPGA to define the supported Resolutions, using AD9887_DDC_SCL and the AD9887_DDC_SDA . That way when an adaptor, such as the PC connects to the VSK, it will automatically know what resolutions are supported by the VSK which in this case is acting as a sink. This circuit uses the AD9887_DDC_SCL and the AD9887_DDC_SDA signals which are connected to the FPGA to program the EEPROM. These signals are also connected to the AD9887, but it does not program the EEPROM, but rather uses these same signals for the HDCP encryption. In this case, the FPGA would do the programming of the EEPROM or the setting up of the HDCP protection.
It should also be noted that the VSK_Diagnostics design has a menu option that allows the user to read and program the J1 EEPROM. The design can also read the EDID of the Monitor that is connected to the DVI output connector. One of the options in the menu allows the user to program the VSK EDID J1 EEPROM with the contents of the Monitors EDID data. There is also a default EDID structure that can be used instead.
2. There are also a set of signal connected to DVI output J2, which would connect to a sink such as a Monitor. My understanding is that a monitor stores some information, that it passes through the TFP410p_DDC_SDA and TFP410_DDC_SCL signals to DVI_OUT_DDC_SDA and DVI_OUT_DDC_SDA which are connected to the FPGA, which would then save the monitor information in a RAM so that it would know what resolutions that the monitor supported.
Also note that the Schematic for this circuit is incorrect. The BSS138N transistors are used for lever shifters. The reason for this is that EEPROM side of the circuit is 5V while the FPGA side is 3.3V. The path through the circuit should be bi-directional.
The VIODC schematic depicts IIC circuits with only unidirectional data flow. The schematics are wrong. Pins 2 & 3 of the BSS138N transistors in both EDID circuits should be swapped. This was realized when the board was being debugged. To fix the problem, the transistors are flipped upside down and the legs bent 180 degrees and soldered to the board. This way pin 1 is still connected to pin 1, pin 2 of the chip connects to pad 3 of the board, and pin 3 of the chip connects to pad 2 of the board. When that is done, the circuit becomes a bi-directional path. All shipped VIODCs should have this hardware fix.