We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 30454

9.2i EDK, MPMC v3.00b - Global Cycle counter in Performance Monitor counts on incorrect clock


The global cycle counter is not counting at the rate expected when using 2:1 Memory to PLB clock ratio. How do I ensure the global cycle counter is valid?


This issue is caused by the global cycle counter running off the incorrect clock, specifically the host PLB control interface clock instead of the memory clock. 


This issue affects MPMC2, MPMC v3, and MPMC v4.00.a. 


You can fix this issue by correcting a single clock process. Copy the MPMC Core to the project directory, and modify the hdl/verilog/mpmc_pm_npi_if.v file as follows: 


line 343: 



always @(posedge Host_Clk) 



always @(posedge PI_Clk) 


This issue is scheduled to be fixed in EDK 10.1 Service Pack 1.

AR# 30454
Date 05/22/2014
Status Archive
Type General Article
Page Bookmarked