The global cycle counter is not counting at the rate expected when using 2:1 Memory to PLB clock ratio. How do I ensure the global cycle counter is valid?
This issue is caused by the global cycle counter running off the incorrect clock, specifically the host PLB control interface clock instead of the memory clock.
This issue affects MPMC2, MPMC v3, and MPMC v4.00.a.
You can fix this issue by correcting a single clock process. Copy the MPMC Core to the project directory, and modify the hdl/verilog/mpmc_pm_npi_if.v file as follows:
always @(posedge Host_Clk)
always @(posedge PI_Clk)
This issue is scheduled to be fixed in EDK 10.1 Service Pack 1.