We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 30472

10.1 ChipScope Pro - Creating PlanAhead project when source files contain ChipScope cores results in "FATAL_ERROR:Portability:basutformat.c:146:1.19"


Keywords: ICON, ILA, VIO, crash, .ngc, translate, FATAL_ERROR:Portability:basutformat.c:146:1.19 - Stack corrupted., LogiCORE ICON (ChipScope Pro - Integrated Controller), LogiCORE VIO (ChipScope Pro - Virtual Input/Output), LogiCORE ATC2 (ChipScope Pro - Agilent Trace Core 2)

When creating a PlanAhead project with source files that contain ChipScope Core files, I receive the following message in ngc2edif:


This occurs using either the CORE Generator or inserter flow. A similar issue can occur when adding core files to a Synplify project. The following message appears:

"@W: Errors during NGC conversion
@N: Reading NGC file "<file_name>.ngc" for timing estimation.
@W: Errors during NGC conversion
@W: NGC files included in project will not be used for timing estimation.
<and later on...>
@E:: Failure during reading EDIF files"


To work around the PlanAhead issue, load the design into PlanAhead before inserting your ChipScope cores.
To work around the issue in Synplify, remove the NGC files from the project.

This is a known issue and is resolved in ISE 10.1 Service Pack 1.
AR# 30472
Date 06/20/2008
Status Active
Type General Article
Page Bookmarked