UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 30517

CORE Generator - Licensing protocol for licensed IP cores

Description

When is a license required?

Does a core need to be regenerated to use an updated license?

If the core was generated with a valid license, does the license need to be found to implement a design using the core?

NGDBuild or BitGen still fails even though I now have a valid license. Why?

Solution

There are four basic licensing levels:

  1. Simulation-only: (Also known as Design Linking) allows a user to create an IP core and simulate the core along with their FPGA design. A configuration file (.bit) cannot be generated with this level of license.
  2. Hardware Evaluation: This license allows an IP core to be generated and simulated. A configuration file for the complete design can be created and loaded into the hardware device. However, the core will stop functioning after a specified amount of time.
  3. Full: A full license grants a user access to a generated netlist of an IP core. The Full license allows the core to be generated, simulated, implemented, and used in an FPGA hardware design.
  4. Source: A Source license grants a user access to the source code of an IP core. The Source license allows the core to be generated, simulated, implemented, and used in an FPGA hardware design.


Licensing information is checked at three different times.

  1. Core generation (CORE Generator)
  2. Translation (NGDBuild)
  3. Configuration (BitGen)


The CORE Generator software always checks the license level before generating a licensed core. The core is generated with the license level that is found. If no license is found, a core is not generated.

NGDBuild checks the license level in which the IP core was generated and also checks the current license level. The lowest common entitlement is used.

Example 1: If a core was generated with a Simulation-only license, but now a Full license is available: NGDBuild sees that the license was created with a Simulation-only license and, even though the current license status is "Full," the netlist is tagged to prevent bitstream generation.
Example 2: If a core was generated with a Full license, but now the license is not available (e.g., expired, network down, using a different computer, etc.), the netlist is tagged to prevent bitstream generation.

In both of the examples above, a warning message is issued stating that a bitstream cannot be created for the design.

BitGen checks the design netlist to determine the license level of IP cores as passed by NGDBuild. If the netlist has been tagged to prevent bitstream generation by any core, a message to that effect is issued and the bitstream is not created.

Example 1: If a core was generated with a Simulation-only license, but now a Full license is available, BitGen fails unless the IP core is regenerated with the current license.
Example 2: If a core was generated and processed through translation (NGDBuild) with a Full license, but now the license is not available (e.g., expired, network down, using a different computer, etc.), BitGen continues since the IP core is regenerated and passed to NGDBuild with the Full license.

To test the license level of LogiCORE IP cores (except for the pci32), in a netlist run 'xlicmgr report <ngc or ngd file name>'.

To check the licensing level of a netlist containing pci32, the netlist would need to be submitted to Xilinx Technical Support to analyze.

For help with licensing, refer to the Xilinx IP Licensing Install Checklist:http://www.xilinx.com/ipcenter/ip_license/ip_licensing_help_checklist.htm

AR# 30517
Date Created 04/09/2009
Last Updated 12/06/2012
Status Active
Type General Article
Tools
  • ISE Design Suite - 12.1
  • ISE Design Suite - 11.1