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AR# 30519

LogiCORE RapidIO - Debugging initialization issues in SRIO core


How do I debug Xilinx SRIO initialization issues?


As with any complex design, it is recommended to run functional simulation to eliminate any design issues prior to system testing. If you need to debug in the hardware, use ChipScope or analyzer to observer following signals:

To check Initialization issue:

port_initialized - Indicates Link training complete; check that it is stable

mode_sel - Combine with port_initialized to determine 4x mode

lnk_rrdy_n/lnk_trdy_n - Indicate status control symbols have been sent/decoded

To check Link Status:

lnk_porterr_n - Indicates the link is in error; suggestion - try external loopback to eliminate the linked partner issue

AR# 30519
Date 02/08/2013
Status Active
Type General Article
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