AR# 30537

10.1 Timing Analysis/Virtex-5 - Why does Timing Analyzer fail to issue a Max Period Warning when I do not have an MREG enabled in the Virtex-5 DSP48E?

Description

Why does TRCE or Timing Analyzer fail to issue a Max Period Warning when I do not have an MREG enabled in the Virtex-5 DSP48E?

Why does my Virtex-5 DSP48E design pass timing, but fail to operate correctly in hardware, when the MREG is set to "0"?

Solution

This is a result of a bug in the timing analysis that fails to recognize when the MREG is set to "0." The result is that the design will not issue a warning until the MAX frequency is reached, which is 450 MHz for a -1 part, instead of the expect 275 MHz.

This issue has been resolved in 10.1 Service Pack 1.

Also see (Xilinx Answer 30538).

AR# 30537
Date 12/15/2012
Status Active
Type General Article