I am using the -4 speed grade device of Spartan-3 AN family. My timing report shows that Tspicko_MISO, which is the "clock to out" time from the CLK pin of SPI_ACCESS to the MISO port, has the delay as 16ns. Is it correct?
This delay value is correct. Tspicko is known as the speed file parameter D_SPI_ACCESS_CLK_MISO. Its value of 16ns comes about in the following way:
prom datasheet value for CLK_MISO 8ns
# MOSI -> pad 6ns
# CSB -> pad 6ns
# CLK -> pad 6ns
# pad -> MISO 2ns
D_SPI_ACCESS_CLK_MISO.delay = T(clk -> pad) + T(CLK_MISO) + T(pad -> MISO) = 6+8+2 =16ns
So the 16ns delay value includes the paths to and from the PROM in the FPGA.