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AR# 30570

PowerPC 440, APU - After a Translation Look-aside Buffer (TLB) miss caused by an instruction fetch, in a very specific combination of events, the APU can lock up or corrupt the data


After a Translation Look-aside Buffer (TLB) miss caused by an instruction fetch, in a very specific combination of events, the Auxiliary Processor Unit (APU) can lock up or corrupt the data.

Refer to (Xilinx Answer 30529) for a list of other Errata.


Category: 4


After an instruction that causes a "special I-side exception", when an APU instruction enters the CPU pipeline, there is a very small probability that the APU can cause the PowerPC 440 to malfunction by locking up or causing data corruption. The main cause of a "special I-side exception" is a TLB miss that is associated with an instruction fetch. Although all of the instructions that enter the CPU pipeline (after an instruction that has caused the "special I-side exception") are flushed, in a very specific situation, the flush of the APU instructions might not be carried out cleanly.

Scenario of Occurrence

The following is an example of a code sequence that can cause this problem:

bcl 29,31,6e34 /* Instr A: jump to last instruction on a page which causes an ITLB miss (Instr B in this case) */



nop /* Instr B: last instruction on the page; causes an ITLB page miss */

sync /* Instr C: new page; hits in the TLB */

nop /* Instr D: hits in the TLB and can be issued to both I/L pipe */

stfs fr25,-7c7e(r20) /* Instr E: APU instruction which causes the hang */

In this example, instruction A is a conditional branch that is predicted correctly to be taken and its target address misses in the TLB. The instruction at the target address of the branch (Instruction B) happens to be the last instruction in the page and the following instruction (Instruction C) is in a new page that happens to hit in the TLB. A few instructions at the beginning of the new page, including the FPU store (Instruction E), may get fetched and enter the CPU pipeline before the exception associated with Instruction B becomes effective. The exception becomes effective when Instruction B reaches the writeback stage and global flush of all the instructions is issued.

It is important to emphasize that even if this sequence exists in the code, this problem might not be encountered. In other words, this is a very rare occurrence.

Software Solutions

To prevent this issue from occurring, use one of the following solutions:

- Use static entries in the TLB. This is typically an attractive way to work around this issue for users who do not use Operating Systems.

- Set CCR0[26] to "1" when an FPU/APU is used. This work-around is implemented mainly by the Operating Systems. There is a slight performance degradation that depends on the application.

AR# 30570
Date 12/15/2012
Status Active
Type General Article
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