When I use a Common Clocks, block RAM-based, FIFO Generator core in a Virtex-5 device, a Synchronous Reset (SRST) assertion does not affect the DOUT or EMPTY outputs from the core as described by the core's User Guide. The DOUT and EMPTY ports are set to the correct state when RD_EN is asserted along with SRST.
This is a known issue that has been reproduced in the v4.2 and v4.3 FIFO Generator cores. A patch is available for this issue, for the FIFO Generator v4.3 Core.
The patch can be downloaded at:
You must take the following steps to install the FIFO Generator core patch:
1. Prior to installing this update, you must install ISE 10.1.
2. Unzip the "fifo_generator_v4_3_cr467318fix.zip" archive to your Xilinx installation directory as pointed to by your Xilinx path variable--for example, "C:\Xilinx10.1\ISE" directory. When extracting, select "Use Folder Names". The archive will ask to overwrite existing files. Please select "Yes to All" and allow it to overwrite these files.