This Release Notes and Known Issues Answer Record is for the Virtex-5-GTP RocketIO Wizard v1.8, released in 10.1, and contains the following information:
- New Features
- Bug Fixes
- Known Issues
- ISE 10.1 design tools support
- Virtex-5 SX240T package support
- IPProtect (secureip) libraries support
- Xilinx ISE Simulator (ISim) support
- SRIO single lane, multilane protocols support
- No error message if design fails to meet timing when using the Perl build script.
- Enable SATA auto-negotiation option not present in Wizard - This option is not available if RXSTATUS encoding format is set to PCI Express.
- Modified GUI wording "Transmitter swing turbo mode" which did not make sense.
- Part selection causes error - Selecting V5LX20T-ff323 results in error.
- Hold-Time work-around not needed for LX20T (Production Silicon).
- Missing design rule - When the TX buffer is bypassed, the Wizard does not ensure individual output dividers are set to 1 and TXCOMM_OUT is used.
- If you set the comma alignment smaller than the datapath width, incoming data can be aligned to multiple positions. The example design does not account for this, and could indicate errors even though data is being received correctly.
- In the case of Clock correction, the GTP wrapper in the Example design is configured correctly but the block RAM data does not have embedded Clock-correction characters.
- In ES silicon, the logic added to make TX timing more reliable, timing closure at fabric rates of 312.5 MHz and higher might require significant effort. For best results, use a 16- or 20-bit interface for line rates higher than 1.25 Gbps.
- There is an issue with 10.1 where designs which use GREFCLK fail with a DRC error. To work around this, an environment variable called XIL_MAP_NO_GT_CLKIN_DRC needs to be set. Please refer to (Xilinx Answer 25316) for more details. This variable has been set in the "build_script.pl" for designs using GREFCLK.
- RX buffer bypass in Oversampling mode is not supported.