AR# 30577

Virtex-5 GTX RocketIO Wizard v1.2 - Release Notes and Known Issues for 10.1


Keywords: core, CORE Generator, ISE, installation, IP, update, GTX, wizard

This Release Notes and Known Issues Answer Record is for the Virtex-5 GTX RocketIO Wizard v1.2 and contains the following information:

- New Features
- Bug Fixes
- Known Issues


New Features

- Added support for the GTX_DUAL transceiver in Virtex-5 FTX devices
- ISE 10.1 design tools support
- DFE support enabled

Bug Fixes

- None at the time of release.

Known Issues

- GTX Wizard 1.2 might not set the following attributes to their optimum value:

Refer to UG198 for the optimum values:

- The TX Phase Alignment circuit generated by the GTX Wizard v1.2 might not work under certain system level conditions and data rates. Refer to "TX Buffering, Phase Alignment, and TX Skew Reduction" in Chapter 6, Section 1 of UG198 for more details on the Phase Alignment recommendations.
- The GTX Wizard v1.2 imposes a Max limit of 312 MHz on the Reference Clock. To generate a design for 312.5 MHz, generate a design with 156.25 MHz and modify the following GTX_DUAL attributes:

In most cases, this will be done for XAUI. If so, the OOB_CLK_DIVIDER attribute does not necessarily need to be changed since XAUI does not use OOB signaling.

- Synplify 8.9 does not handle the GTX_DUAL primitive correctly, which causes the design to error out in NGDBuild with width mismatch errors for some of the attributes.
-- The work-arounds in the wizard for these issues are as follows:
* Block boxing the GTX_DUAL primitive
* Setting some of the GTX_DUAL attributes in the UCF.
-- When the wrappers are ported to your design, the attributes in the UCF will require porting as well.

- In 10.1, for designs using GREFCLK, an environment variable called XIL_MAP_NO_GT_CLKIN_DRC needs to be set. Refer to (Xilinx Answer 25316) for more details. This variable will be set in the for designs using GREFCLK.

- For some of the designs, timing closure at fabric rates of 312.5 MHz and higher might require significant effort. For best results, use a 16/20/32/40 bit interface for line rates higher than 2.5 Gbps.

- For VHDL designs using Synplify 8.9, the GTX Tile wrapper Black boxes the serial ports RXN0, RXP0, TXN0, TXP0, RXN1, RXP1, TXN1 and TXP1.
During implementation, MAP issues warnings that these serial ports are not bonded out. These warnings can be ignored; the design will still work in hardware.
To prevent these warnings, you can comment out the following lines in the GTX Tile Wrapper file.
attribute black_box_pad_pin : string;
attribute black_box_pad_pin of GTX_DUAL : component is "RXN0,RXP0,TXN0,TXP0,RXN1,RXP1,TXN1,TXP1";

AR# 30577
Date 05/16/2008
Status Active
Type General Article