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AR# 30605

ISE simulator - "Error : Simulator - Cannot find hierarchical name glbl.GSR"


When I try to simulate my VHDL design using ISE simulator, I receive the following errors:

ERROR: Simulator - Cannot find hierarchical name glbl.GSR
ERROR: Simulator : 34 - Elaboration failed

Why does this occur?


If you have instantiated any of the Xilinx Library primitives in your design, and you do not have the UNISIM library declaration in your code, ISE Simulator will automatically call the Verilog models. But the Verilog models use GLBL to simulate the GSR, and the GLBL file does not get compiled in the design because the design is a VHDL-only design.

To resolve the issue, please copy the following two statements and paste them before the entity declaration in your VHDL code:

Library UNISIM;

use UNISIM.vcomponents.all;
AR# 30605
Date 12/15/2012
Status Active
Type General Article
  • ISE - 10.1
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • More
  • ISE Design Suite - 11.3
  • ISE Design Suite - 11.4
  • ISE Design Suite - 11.5
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2
  • ISE Design Suite - 12.3
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