This Release Notes and Known Issues Answer Record is for the Endpoint Block Plus Wrapper v1.7 and v1.7.1, released in ISE 10.1 IP Update 1 (IP_10.1.1), and contains the following information:
- General Information
- New Features
- Bug Fixes
- Known Issues
For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at:
IMPORTANT: All users must download and install the v1.7.1 patch found in (Xilinx Answer 30124). This patch fixes some critical issues in v1.7. Note that v1.7 is not up-to-date and is actually older than the v1.6.1 release. The resolved issues and known issues below correspond to the v1.7.1 release.
As of the ISE 9.1i SP4 IP Update 2 release, the LogiCORE Endpoint Block Plus for PCI Express requires a license to generate and implement the core. There is no charge for this license.
To obtain the license, visit the product lounge at:
CR447830 - The expansion ROM BAR is now permanently disabled. The core will return a completion with UR if this BAR is accessed. If you need access to the Expansion ROM BAR, please open a case with Xilinx Technical Support and reference this CR number.
There are three main components to the Endpoint Block Plus Wrapper for PCI Express:
- Virtex-5 FPGA Integrated Block for PCI Express
- Virtex-5 FPGA GTP/GTX Transceivers
- Block Plus Wrapper FPGA fabric logic
There are known issues and restrictions for each of these components, as described below:
Virtex-5 FPGA Integrated Block for PCI Express Known Restrictions
Refer to the "Virtex-5 Integrated Endpoint Block for PCI Express Designs User Guide"
(UG197 - v1.2, December 13, 2007), for a list of Known Restrictions for the Integrated Block. This information is included in Chapter 4, in the "Known Restrictions" section, on page 76. This guide is located at:
Virtex-5 FPGA GTP/GTX Transceivers
Block Plus Wrapper FPGA fabric logic
- CR 456000 - Link capability register bits 10 and 11 are set incorrectly. These bits indicate the level of active state power management support. They should be set to 01 instead of 11. This is scheduled to be fixed in v1.7. To fix this issue, you can override the attribute on the Virtex-5 Block for PCI Express by adding the following to the UCF file:
INST "ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep" LINKCAPABILITYASPMSUPPORT = "01";
- CR 468765 - See (Xilinx Answer 30668)
- CR 469909 - The v1.7.1 Block Plus Endpoint Wrapper for PCI Express uses the TX Buffer Bypass mode for all device configurations (LXT, SXT, and FXT). When using TX Buffer Bypass, it is possible that as the parts temperature significantly increases or decreases, the TX phase alignment performed initially might fail, causing link failure or other stability problems. This issue will be fixed for LXT and SXT in the v1.8 release, and the FXT fix will be in a later version (the date is yet to be determined). If this problem is experienced, issuing a system reset (asserting the sys_reset_n input to the wrapper) will cause TX phase alignment to initiate again.
CR472588 - When the Integrated Endpoint Block for PCI Express in x8 configuration receives two ACKs back-to-back with identical sequence numbers and concurrently the block is in the process of loading a TLP into the Retry buffer, the state machine controlling retry buffer can go into an undesirable state, leading to a transmit lockup condition. While it is legal for a device to send two successive ACKs with the same sequence number, it is not a frequent occurrence. This problem was discovered only when interoperating with the Intel i5000p chipset and has not been seen on other platforms. Xilinx is currently validating a work-around for this problem to be added to the Endpoint Block Plus Wrapper for PCI Express v1.8 released as part of 10.1 IP Update 2 in June 2008.
PIO Example Design
- CR 444221- The PIO RX engine file contains two PIO_64_RX_MEM_RD64_FMT_TYPE state declarations. This should not cause a problem as the synthesis tool ignores the second definition. If it does cause issues, remove the second declaration in the FSM.
- CR 466393 - The PIO TX engine state PIO_64_TX_CPL_QW1 final else statement points to the PIO_64_TX_CPLD_QW1 state. Instead, it should point to PIO_64_TX_CPL_QW1. It should remain in the PIO_64_TX_CPL_QW1 until one of the previous conditions is satisfied and then it returns to the initial state, PIO_64_TX_RST_STATE.
- See (Xilinx Answer 29294) regarding long simulation times for link training.
- CR 452484: Some x1 and x4 UCF files use MGT Clock input pins beside unused MGTs. The UCF files are structured such that the x1 and x4 are subsets of the x8 UCF files. In the x8 UCF files, all the GTPs beside the clock input pins are always in use, but in some x1 and x4 designs, this might not be the case. The GTP User Guide states that the clock should not be input beside an unused MGT. This can cause unpredictable clock issues. Xilinx recommends that you use the CORE Generator RocketIO wizard to create a dummy GTP incantation for the GTP beside the clock input if it is not being used by PCI Express. Refer to the GTP User Guide (UG196) for more information:
The Block Plus Core UCF files are being corrected so that this does not occur.
- CR472341: See (Xilinx Answer 30888) to obtain a x8 UCF for the XC5VLX30TFF665-1.
- Some x1, x4, and x8 designs might not meet timing with the default MAP and PAR settings. To obtain timing closure, you might be required to use multiple PAR seeds or floorplanning. By using Multi-Pass Place and Route (MPPR), you can try multiple cost tables to meet timing. For more information on using MPPR, see the Development System Reference Guide in the Software Manuals found at:
You might also need to floorplan and add advanced placement constraints for both your design and the core to meet timing.
06/23/2008 - Corrected GTP/GTX AR reference to (Xilinx Answer 31207) instead of 30632
06/18/2008 - Moved GTP/GTX issues to (Xilinx Answer 31207).
05/06/2008 - Added CR 472341
05/05/2008 - Added CR 472588
04/25/2008 - Initial Release