This Release Notes and Known Issues Answer Record is for the Virtex-5 FXT FPGA RocketIO GTX Wizard v1.3 and contains the following information:
- New Features
- Bug Fixes
- Known Issues
- Added support for the GTX_DUAL transceiver in Virtex-5 FTX FPGAs
- ISE 10.1 design tools support
- DFE support enabled
- There is a change to the supported range of the OOBDETECT_THRESHOLD attribute. The supported range is limited to 110-111 (000-101 is not supported). 111 is the recommended default. Refer to UG198 v1.1 for more details:
GTX Wizard 1.3 does not set the OOBDETECT_THRESHOLD_0/1 attribute correctly. Set this attribute to 111 for the best results. This issue will be fixed in the next release.
- The TX Phase Alignment circuit generated by the GTX Wizard v1.3 might not work under certain system level conditions and data rates. Refer to "TX Buffering, Phase Alignment, and TX Skew Reduction" in Chapter 6, Section 1 of UG198 for more details on the Phase Alignment recommendations.
- For some of the designs that use RXRECCLK to source RXUSRCLKs, ChipScope ILA might have incorrect RXDATA. This issue will be fixed in the next release.
- Synplify 8.9 does not handle the GTX_DUAL primitive correctly, which causes the design to error out in NGDBuild with width mismatch errors for some of the attributes.
-- The work-arounds in the wizard for these issues are as follows:
* Block boxing the GTX_DUAL primitive
* Setting some of the GTX_DUAL attributes in the UCF.
-- When the wrappers are ported to your design, the attributes in the UCF will require porting as well.
- For some of the designs, timing closure at fabric rates of 312.5 MHz and higher might require significant effort. For best results, use a 16/20/32/40 bit interface for line rates higher than 2.5 Gbps.