AR# 30638

Project Navigator - Adding HDL source to project incorrectly marks process status as out-of-date


After running any of the synthesis or implementation processes, I add a new Verilog or VHDL source to the project using one of the following methods:
  • Project -> Add Source...
  • Project -> Add Copy of Source ...
  • Project -> New Source ...

Even though the added HDL source is not part of the hierarchy of the implemented top-level design, the completed processes are marked out-of-date.

Additionally, with the Add Source and Add Copy of Source processes, even if I select the Cancel option in the Adding Source Files ... window, the processes are still out-of-date.

Adding schematic, IP core, and HDL testbench sources does not set the status of processes out-of-date.


The operation to check the HDL source files does not check based on the hierarchy of the design, and consequently, sets the status as out-of-date (incorrectly in many cases) any time an HDL file is added (or parsed for adding) to a project.

In ISE 10.1 and later, if the added file does not affect the top-level design and the design has not otherwise changed, you can safely force the status of a process and continue implementation from the subsequent process. This can be done by choosing the process to force and select Process -> Force Process Up-to-Date.
AR# 30638
Date 12/15/2012
Status Active
Type General Article