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AR# 30648

10.1 Virtex-4 PAR - "WARNING:Par:100 - Design is not completely routed."

Description

Keywords: EMAC, PPC, reportgen, par, unrouted

My design failed to route successfully. At the end of the PAR report, I see the line:

"1 signals are not completely routed."

How can PAR get so close to routing a design without succeeding? What can I do to ensure that PAR is successful for my design?

Solution

If a design has only one or only several unrouted nets at the end of routing, the problem is probably not due to general congestion but to a specific resource usage issue:

1. A routing connection may depend on a specific relative placement between two components so that a dedicated routing resource can be used. Examples include:

- Carry chain connections between slices
- Shift chain connections between slices
- Dedicated connections between slices for wide gate structures
- Bus connections between DSP48 components
- IPAD connections to GTX component

2. In other cases, a routing connection may depend on the successful management of a limited, shared routing resource. Examples include:

- Shared clock connections on paired IOB sites
- Shared control signal connectivity between paired ILOGIC and OLOGIC sites
- Shared input connections on paired BUFGMUX sites
- Limitations on the number of global clock domains per clock region
- Limitations on the number of output muxes available per CLB tile
- Limitations on the number of global signals on non-global pins per CLB

To determine the root cause of routing failure for a specific net, the NCD written by PAR can be examined in FPGA Editor. Unrouted nets can be found by setting the List Window to "Unrouted Nets" and then selecting any nets in the list to highlight them. If there are more unrouted nets listed than expected, that might be due to the existence of loadless nets which are not reported by PAR. Use the Fanout tab to sort the loadless nets to the bottom of the list. For the unrouted nets with fanout greater than 0, examine the connectivity displayed, taking into account the component and pin types involved and the relative placement, and compare to the known problem areas listed above.
AR# 30648
Date Created 12/04/2008
Last Updated 12/03/2008
Status Active
Type General Article