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AR# 30651

10.1 Timing Analyzer -The maximum frequency of some DSP designs are overestimated


Some Virtex-5 test cases have shown that the reported performance of the DSP48E is faster than achievable in silicon. 


The problem was that trce was analyzing the wrong path since the CARRYIN was tied to ground. It turns out that trce was only trying to analyze a path from CLK -> PCOUT, and it was the delaycalculator that returned the CARRYINREG -> PCOUT path to trce. The root cause of this error stems from the spreadsheets being underspecified.


This problem has been fixed in the latest 10.1 Service Pack 2 available at: 


AR# 30651
Date 05/22/2014
Status Archive
Type General Article