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AR# 30674

10.1 EDK - Platgen errors out when ppc440_mc_ddr2 DWIDTH is less than 64-bits

Description

When I attempt to generate an XPS design for Virtex-5 FXT with a PowerPC and a 32-bit DDR2 interface, PlatGen errors out as below.

Selecting an external data width of 32 bits in the ppc440mc_ddr2 controller seems to force it to use 64-bit connections with the ppc440. However, the ppc440 expects 128-bit wide connections, as hard-coded in the MPD file:

PORT MCMIREADDATA = MCMIREADDATA, DIR = I, VEC = [0:127], BUS = PPC440MC

PORT MIMCWRITEDATA = MIMCWRITEDATA, DIR = O, VEC = [0:127], BUS = PPC440MC

PORT MIMCBYTEENABLE = MIMCBYTEENABLE, DIR = O, VEC = [0:15], BUS = PPC440MC

How does one create a design with an external memory interface less than 64-bits wide?

Solution

This problem has been fixed in the latest 10.1 Service Pack, available at:

http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is 10.1 Service Pack 2.

AR# 30674
Date Created 07/10/2008
Last Updated 12/15/2012
Status Active
Type General Article