When I attempt to generate an XPS design for Virtex-5 FXT with a PowerPC and a 32-bit DDR2 interface, PlatGen errors out as below.
Selecting an external data width of 32 bits in the ppc440mc_ddr2 controller seems to force it to use 64-bit connections with the ppc440. However, the ppc440 expects 128-bit wide connections, as hard-coded in the MPD file:
PORT MCMIREADDATA = MCMIREADDATA, DIR = I, VEC = [0:127], BUS = PPC440MC
PORT MIMCWRITEDATA = MIMCWRITEDATA, DIR = O, VEC = [0:127], BUS = PPC440MC
PORT MIMCBYTEENABLE = MIMCBYTEENABLE, DIR = O, VEC = [0:15], BUS = PPC440MC
How does one create a design with an external memory interface less than 64-bits wide?
This problem has been fixed in the latest 10.1 Service Pack, available at:
The first service pack containing the fix is 10.1 Service Pack 2.