The long local clock route delays in these larger devices results in the data valid window being exceeded in read data timing analysis.
Because of this 133 MHz is not achievable in the XC3S2000, XC3S4000, and XC3S5000 devices for top and bottom bank configurations.
Left and right bank selection designs are not affected by these long local clock route delays, so the frequency support is as shown in the MIG GUI and the MIG User Guide.
The minimum frequency for DDR2 devices is 125 MHz.
Therefore, these larger Spartan-3 devices cannot be supported with top and bottom bank configurations.
Left and right banks must be used.
For DDR, the maximum frequency for the XC3S2000, XC3S4000, and XC3S5000 devices is 110 MHz when top and bottom banks are selected.
Note: Issues are only seen when the data bus is located in top and bottom banks.
There are no issues when the data bus is located in left and right banks, and the address and control are located in the top and bottom banks.
This issue is resolved in MIG v2.3.