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AR# 30684

10.1 EDK, LMB BRAM Controller v2.10a - why LMB of 2 KB not supported

Description

I am creating an EDK design with MB V7.0 and DDR and LMB memory. The target device is a Spartan-3E.

The LMB memory should be as small as possible - so I have chosen 2 Kb.

But now I get the following error:

ERROR:MDT - IPNAME:lmb_bram_if_cntlr INSTANCE:dlmb_cntlr

-

C:\mb_BRAM\system.mhs line 98 - Memory of data width 32-bit and memory size 2-kBytes

does not fit in a fixed size.

Only the following memory configurations are supported:

-----------------------------------------------------------------

| Memory (kBytes) | Memory (kBytes)

Architecture | 32-bit data | 64-bit data

| byte-write | byte-write

-----------------------------------------------------------------

Spartan-II | 2 4 | 4

Spartan-IIE | 2 4 8 16 | 4 8 16 32

Spartan-3 | 8 16 32 64 | 16 32 64 128

Spartan-3E | 8 16 32 64 | 16 32 64 128

Spartan-3A | 2 4 8 16 32 64 | 4 8 16 32 64 128

Spartan-3ADSP | 2 4 8 16 32 64 | 4 8 16 32 64 128

QPro Virtex | 2 4 8 16 | 4 8 16 32

QPro Virtex-E | 2 4 8 16 | 4 8 16 32

QPro Virtex-II | 8 16 32 64 | 16 32 64 128

QPro-R Virtex | 2 4 8 16 | 4 8 16 32

QPro-R Virtex-II | 8 16 32 64 | 16 32 64 128

Virtex | 2 4 8 16 | 4 8 16 32

Virtex-E | 2 4 8 16 | 4 8 16 32

Virtex-II | 8 16 32 64 | 16 32 64 128

Virtex-II PRO | 8 16 32 64 | 16 32 64 128

Virtex-4 | 2 4 8 16 32 64 128 | 4 8 16 32 64 128 256

Virtex-5 | 4 8 16 32 64 128 256 | 8 16 32 64 128 256 512

The same happens for the second LMB.

I do not understand why this is the case.

I can use at least one BRAM in the following layout:

36 bit wide * 512 addresses

This is exactly the 2 Kb size and requires only one block RAM - so why do I not need larger block RAMs?

Why do I need a minimum size of 8 Kb for a Spartan-3E?

Of course byte writes will not work - but this is not a problem in my project.

Solution

For the Spartan-3/3E family, there is only one write enable for each block RAM. So you need 4 block RAMs in order to implement byte enable on the 32-bit bus and therefore a minimum of 8 Kb is required for the block memory size.

If byte writes are not required, it is possible to work around it, but it will require some work. First, on the design tool side, you must make sure there is no byte/half-word access to the block RAM including all drivers and libraries. The second thing is on the hardware side, you will need to rewrite the lmb block RAM controller to somehow combine the byte enable to always write 32-bit words.

There is one other caution. With the original block RAM in EDK, Platgen determines the block memory organization based on the device being used. If you want to use only 1 block RAM in 512x32/512x36 format, you must write your own block RAM to do that as well (or merge it into your custom lmb block RAM controller).

This is similar to the block RAM size limitation for the other device families.

AR# 30684
Date Created 05/19/2008
Last Updated 12/15/2012
Status Active
Type General Article