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AR# 30782

MIG v2.2 - Updating a MIG v1.73 or earlier design requires manual modification to the updated UCF/RTL files to account for the CQ_n (CQ#) pins

Description

The Virtex-5 QDRII design (from MIG 1.73 or earlier) did not contain CQ_n (CQ#) pins for x18 memory devices. Starting with MIG v2.0, the CQ_n pins for x18 memory devices are included in the Data Read banks. There is no logic associated with the CQ_n (CQ#). However, the pins are now available to users who want to make the required changes to implement a CQ/CQ_n design.

These pins were not present in previous releases, therefore, the design/UCF generated by the Update UCF feature in MIG caused errors. The UCF does not contain the CQ_n pins, because it updated a MIG 1.73 UCF. However, the generated RTL code contains the CQ_n pins. The errors are experienced during Translate.

Solution

This issue can be resolved using one of the following workarounds:

Resolution 1:

Comment out the attributes related to CQ_n (CQ#) pins in the updated UCF, as well as the CQ_n (CQ#) port declaration in the design top rtl file. This solution is applicable for users not wanting to use the CQ_n (CQ#) pins.

Resolution 2:

Manually allocate LOC constraints for the cq_n (CQ#) pins in the updated UCF. No additional changes are required.

This issue is resolved in MIG 2.3.
AR# 30782
Date Created 04/15/2008
Last Updated 05/20/2014
Status Archive
Type General Article
Devices
  • Virtex-5 FXT
  • Virtex-5 LX
  • Virtex-5 LXT
  • More
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Virtex-5Q
  • Virtex-5QV
  • Less
IP
  • MIG