When generating an x18 36-bit QDRII design for Virtex-5, if the two Data Read banks are selected in two different columns, the generated UCF file contains the wrong DCI Cascade settings.
This causes the following error during BitGen:
Manual modification is required.
Starting with MIG 2.3, the Memory Interface Solutions User Guide (UG086) includes the appropriate steps to follow regarding this issue.
To accommodate a QDRII Virtex-5 36-bit data width design with x18 parts, two banks are required - 18-bits in each bank.
There are two options for bank selections, selecting banks in the same column or two different columns.
By default, MIG enables the option "DCI Cascade" in either case.
If you select the two Read Data banks in the same column, one of the selected read banks (or any other bank in the same column) can be selected as the Master Bank.
Either option is viable and causes no issues.
If you select the Read Data banks in two different columns, a Master Bank must be selected in each column.
Because MIG has enabled the "DCI Cascade" option, if you select the Read Data bank as the Master Bank, then the Master Bank and Slave Bank would be same.
The syntax for Master bank is as follows:
DCI_CONFIG = "Master bank number Slave bank number;"
In the above case, since the Master bank and Slave bank are the same, the syntax in the MIG output UCF file is as follows:
DCI_CONFIG = "18 18"; (assuming that bank 18 is selected for Data Read)
Selecting the Master and Slave banks in the same bank is not a valid configuration.
This causes BitGen to fail with the following error:
You can use one of the following methods to work around this issue: