UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 30794

MIG v2.3 - Spartan-3 Generation DDR design does not support burst length=2

Description

The Spartan-3 Generation DDR MIG design lists support for designs with a Burst Length of 2 .

However, there is a problem with this type of design in which single cycle reads contain incorrect data.

Due to lack of usage of this particular design feature, the BL=2 design will not be fixed.

This design will be removed from MIG and no longer supported. 

Starting with MIG v3.0, this information has been moved to the MIG User Guide.

Please refer to the user guide for full details.

Solution

When the memory BL is set to 2 and a single cycle read is performed, the data is not correct.

A portion of the data for each read is a byte from a previous read.

Below is an example of what you will see when performing a single cycle read: 

Expected Pattern : 

0x01020304 
0x05060708 
0x090a0b0c 
0x0d0e0f10 

Actual Pattern: 

0x010203xx - Where xx is based on some previous read back value 
0x05060704 - The last byte belongs to the previous read 
0x090a0b08 - The last byte belongs to the previous read 
0x0d0e0f0c - The last byte belongs to the previous read 

The issue is that fifo1_wen does not reset properly and remains asserted.

The deassertion of fifo1_wr_en relies on the last rising edge of dqs_delayed_col0.
AR# 30794
Date Created 04/17/2008
Last Updated 08/12/2014
Status Active
Type General Article
Devices
  • Spartan-3
  • Spartan-3A
  • Spartan-3A DSP
  • More
  • Spartan-3AN
  • Spartan-3E
  • Less
IP
  • MIG