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AR# 30796

MIG v2.2, Spartan-3 Generation DDR2 - Issue with write/read pointer algorithm might cause a loss of FIFO data


In Spartan-3 Generation designs, the read data is captured into FIFOs using DQS.

Each FIFO has a read pointer and a write pointer.

The write pointer is incremented using DQS and the read pointer is incremented with clk90.

To generate the FIFO empty status, the read and write pointers are compared.

When the FIFO is not empty, the "Data Valid" signal is generated and you can start reading the data.

An issue occurs with this algorithm because it compares two pointers that are in two different asynchronous domains.

The comparison is done in the clk90 domain.

The write pointers are registered three times using clk90, and the third register is compared with the read pointer.

Consequently, if the first register goes to a metastable state, there is a possibility of latching the wrong value.

The write pointers would receive incorrect values and as a result, the FIFO data would be lost.


To work around this issue, the write and read pointer compare logic needs to be replaced with a new algorithm. 

After the read command is issued, the new algorithm waits a fixed delay of time before reading the FIFOs (this is to prevent incorrect data being latched).

Implementation Details 

  1. A signal read_fifo_rden is generated in the clk90 domain.
    This signal is set to "1" approximately four clocks after the generation of the rst_dqs_div signal.  
  2. Current FIFO empty generation logic is not used. 
  3. Current write pointer implementation remains as is, but it is not compared with read pointers.
    Consequently, the write pointers are not required to cross the DQS domain to clk90 domain. 
  4. A new flag, read_fifo_rden, is generated in the controller module in the clk180 domain.
    The condition to generate this new flag is the same as the condition that generates the rst_dqs_div_int flag in the controller module except for the clocks.
    The signal rst_dqs_div is generated on clk0 and this new flag is generated on clk180.
    The last "always" block in the comp64_controller_0.v module generates the read_fifo_rden flag.  
  5. This new flag is pipelined three times with clk90 in the comp64_data_read_controller_0.v module (this is u_data_val_r).
    Three pipelines ensure that the read data from memory is written to the FIFOs.
    The signal u_data_val_r is the enable signal to the FIFO read pointers. 
  6. This approach does not require any synchronization of signals by reading the FIFOs a fixed number of clocks after the read command is issued.


This issue is resolved in the MIG v2.3 release. 

In the meantime, you must make changes to the following four RTL files to incorporate the resolution manually: 

  • Controller 
  • Top 
  • Data_Path 
  • Data_Read_Controller 

Logical modifications are made only to the controller and data_read_controller files.
Only the top and data_path files are modified to include the appropriate port connectivity.

Summary of Changes 


New flag "read_fifo_rden" is generated and brought to the output port.
This flag is generated with clk180 in the last "always block" and has the same timing as rst_dqs_div.
See the comment in the attached RTL controller files.


Signal read_fifo_rden is input from Controller.v/.vhd.
The signal is then pipelined three times in the clk90 domain using the signals read_fifo_rden_90r1, read_fifo_rden_90r2, and read_fifo_rden_90r3.
The read_fifo_rden_90r3 signal is then assigned to the read_valid_data_0_1 signal.


No logic changes are made within these files; only port mappings of the read_fifo_rden are added in the instantiations.

The ZIP file below contains an example RTL with the fix.
These files should be used as reference when manually modifying a user MIG output, rather than copying and replacing:  



AR# 30796
Date 08/21/2014
Status Active
Type General Article
  • Spartan-3
  • MIG
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