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AR# 30815

10.1 SimPrim, Timing Simulation - Post PAR simulation does not work as expected

Description

Keywords: Timing, simulation, data, corruption, Post PAR, unexpected

Post-PAR simulation does not work as expected. The data is incorrect or is corrupted, but there is no Setup or Hold error in the Simulator Console or in TRACE.

Solution

This issue might be caused by the Negative Setup and hold window in timing simulation. This phenomenon occurs in post-PAR simulation because the observation point in timing simulation is different than the silicon characterization point.

Figure 1. Illustrates the Negative Setup
Figure 1. Illustrates the Negative Setup


In this example, the characterization in the silicon (delay measurements) is performed at the slice level, but the signal is actually observed at the flip-flop in timing simulation, as illustrated in Figure 1a.

In reality, the flip-flop does not have a negative setup but the silicon characterization done at the slice level shifts the setup window for the flip-flop (Figure 1a). As a result, the data at the silicon boundary is allowed to change after the clock edge as long as it is before the negative setup window (Figure 3c). This phenomenon causes the SDF file to include negative numbers for the setup window

Figure 2. Illustrates an Example Negative Hold Condition
Figure 2. Illustrates an Example Negative Hold Condition


Figure 2b shows how the data is processed by the flip-flop with respect to the slice in silicon. This means that in timing simulation, the data is allowed to change before the clock edge as long as it is after the negative hold window.

If there are Negative Setup numbers, then the window is shifted to the right of the clock edges as shown in Figure 3(c). Consequently, the data that occurs after the clock edge is used.

If there are Negative Hold numbers, then the window is shifted to the left of the clock edges as shown in Figure 3(b). Consequently, the data that occurs before the clock edge is used.

Figure 3. Illustrates the Shift in SETUP/HOLD Window
Figure 3. Illustrates the Shift in SETUP/HOLD Window


What Occurs in Timing Simulation?

If there is negative setup and hold, there is the possibility of receiving incorrect simulation results if the design has very little slack. The problem that might occur with timing simulation is illustrated in Figure 4. The models currently do not take into account the negative setup or negative hold window when clocking data. The model clocks the data present at the clock edge and does not factor in the negative setup or hold window. This can result in incorrect clocking of data, leading to unexpected simulation results or data corruption. The simulator does not issue a warning unless the data changes in the setup or hold window. In this case, there are no warnings or errors, but there is incorrect data.

In Figure 4, the data processed by the silicon is not equal to the data processed by the simulation model, but the simulator does not error out with a setup violation because the data was stable in the negative setup window.

Negative Hold -> data can change before the clock edge
Negative Setup -> do not see the actual data until after the clock edge

Figure 4.
Figure 4.


Why does Negative Setup/Hold not affect TRACE?

The timing for the timing simulation works as expected. The timing windows are properly created and if you have a timing violation within the timing window, it will be reported.

This issue is related to data corruption, and not timing validity. For static timing analysis, it is an equation in which numbers are plugged in to, and if you ask for less time than the equation derives, it flags a violation. Timing simulation is definitely different in many respects, but the one to key point is that it not only validates timing but also the data, and it is the second component that static does not address. The root cause of the data corruption has to do with how timing models are created, which forces a "strange" situation in simulation. For static timing analysis, it equates to a negative number in its calculations. However, for timing simulation, it more or less equates to negative time, which is a concept that is not only difficult to grasp in the real world, but is almost as difficult in the simulation world to travel back in time.

The fix for this is to not build a simulation time machine, but to store the value for later in a separate variable and then use it when needed. This fix will be in the Xilinx Simulation library models.

This phenomenon is observed in the following blocks: X_FF, X_SFF, X_LATCH, X_LATCHE, X_RAMD*, X_RAMS*, X_SRL*. Xilinx is actively working on making changes to the Timing simulation models so that the negative Setup and Hold numbers will work better with the simulators. The complete solution in the model will be released in 11.1.
*Different configurations of the block

X_FF, X_SFF, X_LATCH, X_LATCHE models has been fixed in 10.1 Sp2.
(SP2 is scheduled released by the end of June 2008)

Currently, there is a limitation in the Xilinx timing simulation model to handle negative setup/hold that might result in incorrect clocking of data during timing simulation. Xilinx is aware that debugging such a discrepancy is very time consuming. Xilinx recommends performing a static timing analysis and making sure that all paths are covered and the design meets timing before attempting to perform a timing simulation.
AR# 30815
Date Created 04/21/2008
Last Updated 06/19/2008
Status Active
Type General Article