The plbv46_pcie_v2_01_a Core fails timing when used in Base System Builder (BSB) to build a Virtex-5 FXT system in EDK 10.1.1.
The "plbv46_pcie_pkg.vhd" file in the plbv46_pcie_v2_01_a has been modified by changing the MaxPayloadSize to 512 bytes from 2048 bytes. The Virtual Channel 1 (VC1) buffers were set to zero. These two changes eliminate the timing problems when using BSB on an FXT part.
To resolve this issue, you need to make a change a single file. The corrected "plbv46_pcie_pkg.vhd" file that fixes this issue is available at:
Unzip and put the "plbv46_pcie_pkg.vhd" file in the local "pcore" directory as shown below:
These subdirectories must be created manually under <project_directory>/pcores directory.
This issue will be fixed in the next release of the EDK 10.1 SP2.