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AR# 30830

10.1 EDK SP1, plbv46_pcie_v2_01_a - When using Base System Builder to build a Virtex-5 FXT system, the plbv46_pcie Core fails timing

Description

The plbv46_pcie_v2_01_a Core fails timing when used in Base System Builder (BSB) to build a Virtex-5 FXT system in EDK 10.1.1.  

 

The "plbv46_pcie_pkg.vhd" file in the plbv46_pcie_v2_01_a has been modified by changing the MaxPayloadSize to 512 bytes from 2048 bytes. The Virtual Channel 1 (VC1) buffers were set to zero. These two changes eliminate the timing problems when using BSB on an FXT part.

Solution

To resolve this issue, you need to make a change a single file. The corrected "plbv46_pcie_pkg.vhd" file that fixes this issue is available at: 

 

http://www.xilinx.com/txpatches/pub/applications/misc/plbv46_pcie_pkg.zip
 

Unzip and put the "plbv46_pcie_pkg.vhd" file in the local "pcore" directory as shown below: 

 

<project_directory>/pcores/plbv46_pcie_v2_01_a/hdl/vhdl/plbv46_pcie_pkg 

 

These subdirectories must be created manually under <project_directory>/pcores directory. 

 

This issue will be fixed in the next release of the EDK 10.1 SP2.

AR# 30830
Date Created 04/23/2008
Last Updated 05/22/2014
Status Archive
Type General Article