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AR# 30845

10.1 EDK, mch_opb_ddr_v1_00_c - MCH_OPB_DDR controller does unnecessary precharge when accessing the same row address


When using mch_opb_ddr_v1_00_c EDK DDR controller, additional precharges are performed that are not necessary due to the use of open row management. How do I resolve this issue?


This issue might reduce performance but should not cause data errors. This issue is not planned to be fixed since this core is no longer being actively developed.

AR# 30845
Date 05/22/2014
Status Archive
Type General Article
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