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AR# 30872

LogiCORE RapidIO v4.3 - XST port mismatch error can be seen when using VHDL design files


When you generate SRIO Core with VHDL selected as Design Entry option, you might see following synthesis error from XST:

"../example_design/rio_wrapper.v" line 389: In module <rio_wrapper>

ERROR:Xst:2585 - Port <deviceid_o> of instance <log_io_top> does not exist in definition <rio_log_io_v4_3>. Please compare the definition of block <rio_log_io_v4_3> to its component declaration to detect the mismatch.


SRIO Core currently does not provide design files in VHDL. However, if you select VHDL as your Design Entry option, it will give you example design files in Verilog, and provide simulation files in VHDL. When synthesizing the example design files, it uses logi_io_v4_3_bb.v file as black box.

Work-around for the above port mismatch error:

Add following "deviceid_o" declaration to rio_log_io_v4_3_bb.vhd file located in /implement directory.

deviceid_o : out STD_LOGIC_VECTOR ( 0 to 15 );

This issue will be fixed in the next version of SRIO Core.

AR# 30872
Date 12/15/2012
Status Active
Type General Article
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