When I simulate my embedded design, the clock generator does not output any clock signals.
There is an error in the PAO file associated with clock_generator_v2_01_a.
To work around the problem, follow these steps:
1. Open C:\Xilinx\10.1\EDK\hw\XilinxProcessorIPLib\pcores\clock_generator_v2_01_a\data\clock_generator_v2_1_0.pao in a text editor.
2. Change clock_generator_v2_00_a to clock_generator_v2_01_a.
3. Save and close the file.
4. Recompile the EDK simulation libraries.
This problem has been fixed in the latest 10.1 Service Pack available at:
The first service pack containing the fix is 10.1 Service Pack 2.