AR# 3091


Foundation F1.x, Timing Simulator: Same bus name with different indices gives 'X' outputs


Keywords: logic simulator, unknown, label

Urgency: Standard

General Description:

When a label is used for an input bus with one set of indices (eg 15:8) and an output bus with another set of indices (eg 7:0), the timing simulator does not distinguish between the two busses. The result is X outputs for the input bus. Usually, the only signal that can be selected for simulation is a bus of 15:0 as an output.


For example, suppose a design contains an input bus called
MY_BUS[15:8] and an unrelated output bus called MY_BUS[7:0].
Although these are truly 2 separate and unique busses, they
will not be differentiated between in timing simulation. You
will only have the ability to select a bus called MY_BUS[15:0]
and this bus will be an output only.

Currently, the only solution for this problem is to name the 2
busses differently, ie MY_BUSA[15:8] and MY_BUSB[7:0].

AR# 3091
Date 03/07/2002
Status Archive
Type General Article
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