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AR# 30913

ISE Simulator (ISim) - "ERROR: Signal EXCEPTION_ACCESS_VIOLATION"

Description

The following error occurs when I run simulation in ISim:

ERROR: Signal EXCEPTION_ACCESS_VIOLATION received


Why does this occur?

Solution

If your Windows system has the EMBASSY Trust Suite software installed, please read (Xilinx Answer 30666).

To determine whether this software is installed on your machine, either review the list of software available under "Add/Remove Programs" in the Windows Control Panel or contact your IT department.


This situation occurs when ISim has encountered either a software environment or code construct that it does not know how to handle or resolve.


Common causes of this problem in ISE Design Suite 11.4 and newer are as follows:

  • When attempting to disable a Verilog block using a hierarchical statement.

For example:
 
disable Burst_man.pollingBurst;
To work around this issue, use code similar to the following:
 
//use "->Burst_man.disable_pollingBurst;" instead of the original statement "disable Burst_man.pollingBurst;"
//disable Burst_man.pollingBurst;
->Burst_man.disable_pollingBurst;
// add the following code into the submodule in which "pollingBurst" is declared and used
event disable_pollingBurst;
always @(disable_pollingBurst)
disable pollingBurst;
Refer to the attached "worked_around_28F256P30.v" file for the code change in an actual example code.

This issue is fixed in Vivado Simulation.

Common causes of this problem in previous versions of ISE Design Suite that have been resolved in the latest update are as follows:
 
  • When an Attempt is made to generate an SAIF dump file in Windows.
  • When a declared signal is passed down through a VHDL design unit, and then through to a Verilog module of type inout.
  • When driving an output formal signal from a procedure with a wait, which is called from another procedure.

Obtain the latest ISE Design Suite update from the Download Center.

If the above solutions do not resolve the issue, please open a WebCase with Xilinx Technical support and provide a test case so that Xilinx can find a fix or work-around for this problem.
 
WebCase link:
http://www.xilinx.com/support/clearexpress/websupport.htm

Attachments

Associated Attachments

Name File Size File Type
worked_around_28F256P30.v 107 KB V

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
33381 ISE Design Suite 11 - ISE Simulator (ISim) Known Issues N/A N/A
AR# 30913
Date Created 09/11/2008
Last Updated 10/22/2014
Status Active
Type General Article
Tools
  • ISE - 10.1
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • More
  • ISE Design Suite - 11.3
  • ISE Design Suite - 11.4
  • ISE Design Suite - 11.5
  • ISE Design Suite - 12.1
  • Less