This situation occurs when ISim has encountered either a software environment or code construct that it does not know how to handle or resolve.
Common causes of this problem in ISE Design Suite 11.4 and newer
are as follows:
- When attempting to disable a Verilog block using a hierarchical statement.
To work around this issue, use code similar to the following:
//use "->Burst_man.disable_pollingBurst;" instead of the original statement "disable Burst_man.pollingBurst;"
// add the following code into the submodule in which "pollingBurst" is declared and used
Refer to the attached "worked_around_28F256P30.v" file for the code change in an actual example code.
This issue is fixed in Vivado Simulation.
Common causes of this problem in previous versions
of ISE Design Suite that have been resolved in the latest update are as follows:
- When an Attempt is made to generate an SAIF dump file in Windows.
- When a declared signal is passed down through a VHDL design unit, and then through to a Verilog module of type inout.
- When driving an output formal signal from a procedure with a wait, which is called from another procedure.